Gain Error Research Articles

Improving GNSS-R Ocean Wind Speed Retrieval for the BF-1 Mission Using Satellite Platform Attitude Measurements

The receive antenna gain is needed to accurately calibrate the normalized bi-statistic radar cross section (NBRCS) measured by the BF-1 mission, which is a global navigation satellite system reflectometry (GNSS-R) constellation of two microsatellites and the first Chinese GNSS-R satellite mission. The instability of the satellite platform is the main cause of receive antenna gain errors. To obtain a high precision gain value, a calibration method that remaps the ocean surface detection location to the receive antenna pattern using satellite platform attitude measurements is proposed in this paper. Thirty-two orbits of Delay Doppler maps (DDMs) data, which were greatly disturbed by the attitude, are selected to test the effectiveness of the proposed algorithm. The accuracy of wind speed retrieval is analyzed, and results show that the data calibration algorithm is effective in reducing the wind speed retrieval error. Compared with the un-calibrated data, the data subjected to the calibration algorithm show a significant improvement of 19.33% in correlation coefficient and average decreases of 30.91% and 42.57% in root mean square error (RMSE) and mean bias error (MBE), respectively. Moreover, the comparison highlights that the influence of the satellite platform attitude disturbance on wind speed retrieval is abated significantly. The proposed approach can effectively improve the quality of GNSS-R measurements, allowing for a better understanding of global weather abnormalities and generally improving weather forecasting.

Parasitic-Aware Simulation-Based Optimization Design Tool for Current Steering VGAs

Designing millimeter-wave variable gain amplifiers (VGAs) is very challenging owing to the parasitic effects of the interconnects of both active and passive devices. An automated parasitic-aware optimization RF design tool is proposed in this paper to address this challenge. The proposed tool considers the parasitic effects prior to layout. It employs a knowledge-aware optimization technique. The augmentation between parasitic-aware and knowledge-aware techniques speeds up the design process and leads to a design as close to the final design after finalizing the layout. The proposed tool gives limitless and guaranteed converged solutions in a wide range of RF frequencies. A four-bits current steering VGA design is used as a validation of the tool. The tool is tested on three different frequencies using the 65 nm-technology node. The three tested frequencies (7, 10, and 13 GHz) show a root mean square gain error at approximately 0.1 dB and a phase variation at approximately 3.5° within a 16-dB gain control range. To our knowledge, it is the first reported automated design tool for a current steering VGA.

CMOS variable-gain phase shifter based on time-varying vector-sum method and its application to Ku-band phased array

In this paper, a new time-varying vector-sum method is proposed for variable-gain phase shifter design. By introducing a time variable into the conventional vector-sum phase shifter (VSPS) architecture, high-resolution phase shifting and wide amplitude control can be achieved simultaneously. The proposed time-varying phase shifter (TVPS) is fabricated in 0.13-μm CMOS technology with a core area of 1.76 mm2. A field-programmable gate array (FPGA) is utilized to generate gain-control timing sequences for phase shifting and on-off timing sequence for amplitude control, which are optimized to achieve a measured sideband suppression ratio of −17.2 dBc. For bidirectional operation, measured results present that the proposed TVPS can achieve a phase resolution of 10-bits, RMS (root mean square) phase error of 0.2–0.5°, RMS gain error of less than 0.2 dB, and gain tuning range of 10.1 dB in the frequency band of 12–18 GHz. The proposed TVPS is applied to a 4-element phased array, and the measured radiation patterns of scanned beams are presented.

Feature-Sensitive Ring Artifact Correction for Computed Tomography

In computed tomography (CT) reconstruction, ring artifacts emerge from incorrectly normalized or defective detector elements. Correction algorithms often introduce blur or do not correctly accommodate the behaviour of those artifacts. Normalization errors stem from noise in the detector images during the normalization process and are always present to some degree. We propose a method for correcting ring artifacts from incorrectly normalized detector elements in the sinogram. Our approach compensates for errors both in the individual gain as well as offset of pixel values. We reduce blur by inferring gain and offset information for each pixel from its neighbors only in a subset of all projections. We show with datasets from real measurments that our method is effective at mitigating the shortcomings of purely offset based approaches and approaches using all projections. Furthermore, our method can be efficiently implemented compensating for most overhead times. Under usual circumstances, our method can be implemented to function with no additional time overhead at all.

A 60-GHz Variable Gain Phase Shifter Based on Body Floated RF-DAC Structure

In this brief, a 60 GHz variable gain phase shifter based on body floated RF-DAC structure is presented, which is fabricated in 65 nm bulk CMOS process. The proposed variable gain phase shifter consists of I/Q generator and RF-DAC structure based quadrature vector summing amplifier. A low loss and wide band I/Q generator is proposed, which combines a hybrid coupler and a RC poly-phase filter. The vector summing amplifier adapts a pair of RF-DAC structures for each quadrature signal which turn on and off complementarily. This makes the input and output impedances invariant to control states, which are very important characteristics to reduce RMS gain and phase errors of the phase shifter. The RF-DAC cell is implemented with body floated FETs to reduce the Cds at on and off cells for high gain. The RMS gain and phase errors of the proposed phase shifter show 0.13 dB and 0.88°, respectively, at 60 GHz with 3-bits gain control in 8 dB dynamic range, and 5-bits phase control in 360°. In the frequency range of 57 GHz to 62.7 GHz, RMS gain and phase errors show 0.39 dB and 3.01°, respectively. The chip area and overall power consumption are measured to be 0.71 mm2 and 36 mW, respectively.

Simultaneous Bandwidth-Extended and Precisely-Gain-Controlled dB-Linear PGA Based on Active Feedback and Binary-Weighted Switches

A simple yet effective approach for programmable gain amplifier (PGA) with a high precision decibel (dB)-linear characteristic and wide bandwidth is presented in this brief. This novel approach is presented by innovatively combining two techniques. Based on the binary-weighted switching technique, the circuit can approach an accurate pseudo-exponential function without using an additional exponential generator for gain control. By adopting the active feedback circuit structure, the bandwidth of PGA can be extended and it also contributes to improve the robustness, both of which cleverly reached a good consistency. The proposed PGA is fabricated in a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.18~{\mu }\text{m}$ </tex-math></inline-formula> CMOS technology, the core circuit occupies an area of 0.11 mm2. Operated at a supply voltage of 1.8 V, the PGA consumes 8.21 mW. The measurement results show that the voltage gain of the proposed PGA can be controlled from −4.2 dB to 25.9 dB with a gain error less than ±0.09 dB, and the minimum −3dB bandwidth is almost 630 MHz. The input 1dB compression point is measured from −28.7 to 0.5 dBm, while the input referred noise is from 22.4 to 70.9 nV/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${{\sqrt {}}}$ </tex-math></inline-formula> Hz.

Neuromorphic model of hippocampus place cells using an oscillatory interference technique for hardware implementation

In this paper, we propose a simplified and robust model for place cell generation based on the oscillatory interference (OI) model concept. Aiming toward hardware implementation in bio-inspired simultaneous localization and mapping (SLAM) systems for mobile robotics, we base our model on logic operations that reduce its computational complexity. The model compensates for parameter variations in the behaviors of the population of constituent theta cells, and allows the theta cells to have square-wave oscillation profiles. The robustness of the model, with respect to mismatch in the theta cell’s base oscillation frequency and gain—as a function of modulatory inputs—is demonstrated. Place cell composed of 48 theta cells with base frequency variations with a 25% standard deviation from the mean and a gain error with 20% standard deviation from the mean only result in a 20% deformations within the place field and 0.24% outer side lobes, and an overall pattern with 0.0015 mean squared error on average. We also present how the model can be used to achieve the localization and path-tracking functionalities of SLAM. Hence, we propose a model for spatial cell formation using theta cells with behaviors that are biologically plausible and hardware implementable for real world application in neurally-inspired SLAM.

A Versatile ±25-A Shunt-Based Current Sensor With ±0.25% Gain Error From −40 °C to 85 °C

This article presents a versatile shunt-based current sensor for battery management applications. It digitizes the current-induced voltage drop across an external shunt resistor with the help of a 2nd-order delta-sigma ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula> ) ADC, whose summing node is implemented as a low-noise capacitively coupled amplifier. To compensate for the shunt’s finite temperature coefficient (TC), the TC of the ADC on-chip voltage reference can be tuned. As a result, the sensor maintains high accuracy when used with low-cost high TC shunts, such as PCB traces, as well as with more expensive low TC shunts, such as metal-alloy resistors. Optimal gain flatness over temperature is achieved by a two-current room-temperature TC tuning scheme, which exploits the shunt’s self-heating at high current levels. Fabricated in a standard 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS process, the current sensor occupies 0.36 mm2 and draws 265 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{A}$ </tex-math></inline-formula> from a 1.8-V supply. Over the industrial temperature range (−40 °C to 85 °C) and a ±25-A current range, it achieves the state-of-the-art gain error (±0.25%) with both PCB (1.6 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{m}\Omega $ </tex-math></inline-formula> ) and metal-alloy (2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{m}\Omega $ </tex-math></inline-formula> ) shunts. With these shunts, it achieves 5.3-mA/4.3-mA (rms) resolution in a 10-kHz bandwidth.

The Impact of Beam Variations on Power Spectrum Estimation for 21 cm Cosmology. I. Simulations of Foreground Contamination for HERA

Detecting cosmological signals from the Epoch of Reionization (EoR) requires high-precision calibration to isolate the cosmological signals from foreground emission. In radio interferometry, the perturbed primary beams of antenna elements can disrupt the precise calibration, which results in the contamination of the foreground-free region, or the EoR window, in the cylindrically averaged power spectrum. For the Hydrogen Epoch of Reionization Array (HERA), we simulate and characterize the perturbed primary beams that are induced by feed motions, such as axial, lateral, and tilting motions, above the 14 m dish. To understand the effect of the perturbed beams, visibility measurements are modeled with two different foreground components, point sources and diffuse sources, and we find that different feed motions present a different reaction to each type of sky source. HERA’s redundant baseline calibration in the presence of nonredundant antenna beams due to feed motions introduces chromatic errors in the gain solutions, producing foreground power leakage into the EoR window. The observed leakage from the vertical feed motions comes predominantly from point sources around the zenith. Furthermore, the observed leakage from the horizontal and tilting feed motions comes predominantly from the diffuse components near the horizon. Mitigation of the chromatic gain errors will be necessary for robust detections of the EoR signals with minimal foreground bias, and this will be discussed in a subsequent paper.

A 72-dB SNDR 130-MS/s 0.8-mW Pipelined-SAR ADC Using a Distributed Averaging Correlated Level Shifting Ring Amplifier

This article presents a 14-b 130-MS/s two-stage pipelined-SAR analog-to-digital converter (ADC) using a distributed averaging correlated level shifting (DACLS) ring amplifier as its residue amplifier (RA). Compared to the prior CLS and ACLS techniques that reduce the RA gain error due to their finite open-loop gain, the proposed DACLS ring amplifier no longer requires an extra level-shifting capacitor ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$C_{\mathrm {LS}}$ </tex-math></inline-formula> ) at the RA output, such that the RA bandwidth can be improved. Furthermore, instead of a single-level shift in the prior arts, the DACLS ring amplifier provides an option for multiple level shifts and thereby accomplishes a greater RA gain error reduction. In addition, a customized bypass-window scheme is applied, which can skip some power-wasting digital-to-analog converter (DAC) switchings by window detection and thus reduces the power consumption of the ADC. To reduce the bit-cycling time of the SAR conversion, a delay-reduced (DR) SAR logic is introduced to increase the ADC speed. The ADC chip is fabricated in 28-nm CMOS technology and occupies an active area of 0.013 mm2. At 130-MS/s and the Nyquist-rate input frequency, the measured SNDR is 72.5 dB, while the power consumption is only 0.82 mW. Without any calibration, the proposed ADC achieves a Walden and a Schreier figure-of-merit (FoM) of 1.8 fJ/conversion step and 181.5 dB, respectively. Compared to the prior-art ADCs with an input bandwidth ≥ 40 MHz and a SNDR > 68 dB, this work shows the best FoMs.

A Pitch-Matched Transceiver ASIC With Shared Hybrid Beamforming ADC for High-Frame-Rate 3-D Intracardiac Echocardiography

In this article, an application-specific integrated circuit (ASIC) for 3-D, high-frame-rate ultrasound imaging probes is presented. The design is the first to combine element-level, high-voltage (HV) transmitters and analog front-ends, subarray beamforming, and in-probe digitization in a scalable fashion for catheter-based probes. The integration challenge is met by a hybrid analog-to-digital converter (ADC), combining an efficient charge-sharing successive approximation register (SAR) first stage and a compact single-slope (SS) second stage. Application in large ultrasound imaging arrays is facilitated by directly interfacing the ADC with a charge-domain subarray beamformer, locally calibrating interstage gain errors and generating the SAR reference using a power-efficient local reference generator. Additional hardware-sharing between neighboring channels ultimately leads to the lowest reported area and power consumption across miniature ultrasound probe ADCs. A pitch-matched design is further enabled by an efficient split between the core circuitry and a periphery block, the latter including a datalink performing clock data recovery (CDR) and time-division multiplexing (TDM), which leads to a 12-fold total channel count reduction. A prototype of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$8{\times }9$ </tex-math></inline-formula> elements was fabricated in a TSMC 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> HV BCD technology and a 2-D PZT transducer matrix with a pitch of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$160 \mu \text{m}$ </tex-math></inline-formula> , and a center frequency of 6 MHz was manufactured on the chip. The imaging device operates at up to 1000 volumes/s, generates 65-V transmit pulses, and has a receive power consumption of only 1.23 mW/element. The functionality has been demonstrated electrically as well as in acoustic and imaging experiments.

Precise method for accuracy and sensitivity improvement of a current mirror for very low current measurement on a dissolved oxygen biosensor

Dissolved oxygen measurements using an electrochemical biosensor and conventional current mirror with accurate results and the desired sensitivity are difficult to achieve, though this type of current mirror is used frequently to processbiosensor signals, providing a good response. However, it exhibits some drawbacks particularly due to mismatched transistors, which will lead to asymmetry between input and output currents. This asymmetry causes unwanted offset and gain error, reducing its accuracy, especially at very low current. A modified current mirror utilizing precise gate voltage adjustment of FETs is applied to match the transistors’ currents. The results show accuracy improvement of the modified current mirror compared to the conventional current mirror, where the improvements provide a very low accuracy error of 0.01%. In addition, the current mirror’s sensitivity can be adjusted by implementing this modification without increasing noise significantly.

Deep residual neural-network-based robot joint fault diagnosis method

A data driven method-based robot joint fault diagnosis method using deep residual neural network (DRNN) is proposed, where Resnet-based fault diagnosis method is introduced. The proposed method mainly deals with kinds of fault types, such as gain error, offset error and malfunction for both sensors and actuators, respectively. First, a deep residual network fault diagnosis model is derived by stacking small convolution cores and increasing the core size. meanwhile, the gaussian white noise is injected into the fault data set to verify the noise immunity for the proposed deep residual network. Furthermore, a simulation is conducted, where different fault diagnosis methods including support vector machine (SVM), artificial neural network (ANN), convolutional neural network (CNN), long-term memory network (LTMN) and deep residual neural network (DRNN) are compared, and the simulation results show the accuracy of fault diagnosis for robot system using DRNN is higher, meanwhile, DRNN needs less model training time. Visualization analysis proved the feasibility and effectiveness of the proposed method for robot joint sensor and actuator fault diagnosis using DRNN method.

Research on Intelligent Fault Diagnosis of Wind Power Generation System Based on Data Fusion

With the consume of traditional petrifaction energy origin such as coal, matelote and physical gas and the increasingly serious question of entire warming, the penetration ratio of wind power in the energy economy continues to enhance. Wind farms are generally built-in areas with strong winds, tough working environments and a high probability of equipment failure. Faults on large grid-connected wind turbines will seriously influence the safety and stability of conventional strength grids. In addition, unplanned maintenance after a breakdown of wind turbines needs a lot of manpower and corporeal resources, which greatly decrease the efficiency of wind strength production and enhance production costs. Therefore, the key to solving the above problems is to quickly and efficiently identify fan faults, which in turn enables accurate troubleshooting. In the article, the malfunction diagnosis of intelligent wind power system based on data fusion is discussed, and it is found that the GBoost algorithm has high accuracy in detecting sensor gain error, sensor offset error and sensor standard error when the Gaussian white-to-noise ratio exceeds 45 dB. In addition, DBN has different diagnostic effects for different faults with different Gaussian noises, at 45 dB and 35 dB, each type of error varies slightly, and the dotted line varies; at 25 dB, each type of error has a large difference. The difference is large, indicating that at 25 dB, this type of error is more sensitive; comparing the state estimation effect makes DLSTM have good adaptability to time series, and also shows that DLSTM considers the system to be reliable enough, and can be obtained by data fusion of the parameters of each system. What is the state of its system, and then take corresponding measures.

A compact 90–96 GHz 6‐bit passive vector modulator phase shifter in 28‐nm CMOS for phase array applications

AbstractThis letter presents a 90–96 GHz 6‐bit digital control passive vector modulator phase shifter (PS) in a 28‐nm complementary metal–oxide–semiconductor for phase array application. In PS, a full differential directional coupler as a quadrature generator (QG) is proposed, which achieves wide bandwidth and a high‐performance orthogonal network by introducing more pole‐zero pairs. In the vector modulator, two 6‐bit binary‐weighted vector modulators, respectively scale the quadrature signal generated by QG to achieve a high‐resolution vector phase. The measured PS cover and the minimal root mean square (RMS) phase error is and RMS gain error 0.3 dB at 93 GHz, respectively. The fabricated PS occupies excluding pads with no power consumption.

A signal separation method based on the subarray beam synthesis

Large-scale arrays are widely used due to their advantages of high gain, high resolution, and strong beam control capability. The large number of antennas leads to a sharp increase in computational complexity, and thus, it is necessary to reduce the complexity of signal processing. A signal separation method is proposed based on subarray beam synthesis. This method can improve signal reception and separation performance through zero-forcing calculation and realise system gain and phase error corrections in the front end of an antenna. Compared with back-end processing, it has the advantage of low implementation difficulty. The feasibility and performance of the method are verified by simulations.

Low-Cost High-Resolution Potentiostat for Electrochemical Detection of Nucleic Acids and Biomolecular Interactions.

A handheld USB-powered instrument developed for the electrochemical detection of nucleic acids and biomolecular interactions is presented. The proposed instrument is capable of scanning ± 2.25 V while measuring currents up to ±10 mA, with a minimum current resolution of 6.87 pA. Therefore, it is suitable for nucleic acid sensors, which have high background currents. A low-cost microcontroller with an on-chip 16-bit analog-to-digital converter, 12-bit digital-to-analog converter, and a built-in USB controller were used to miniaturize the system. The offset voltages and gain errors of the analog peripherals were calibrated to obtain a superior performance. Thus, a similar performance to those of the market-leader potentiostats was achieved, but at a fraction of their cost and size. The performance of the application of this proposed architecture was tested successfully and was found to be similar to a leading commercial device through a clinical application in the aspects of the detection of nucleic acids, such as calf thymus ssDNA and dsDNA, and their interactions with a protein (BSA) by using single-use graphite electrodes in combination with the differential pulse voltammetry technique.

A 6-Bit 20 GS/s Time-Interleaved Two-Step Flash ADC in 40 nm CMOS

A 6-bit 20 GS/s 16-channel time-interleaved (TI) analog-to-digital converter (ADC) using a two-step flash ADC with a sample-and-hold (S/H) sharing technique and a gain-boosted voltage-to-time converter (VTC) is presented for high-speed wireline communication systems. By sharing one S/H between coarse and fine stages in the two-step flash ADC, the input bandwidth as well as area and power efficiency can be improved without a gain error between coarse and fine ADCs. Thanks to an eight-time interpolation using the gain-boosted VTC, the fine ADC has a small gate capacitance without a speed penalty, even in a small input voltage range. A prototype ADC implemented in a 40 nm CMOS process occupies a 0.1 mm2 active area. The measured differential non-linearity (DNL) and integral non-linearity (INL) after offset and gain calibrations were 0.45 and 0.39 least significant bit (LSB), respectively. With a 9.042 GHz input, the measured signal-to-noise and distortion ratio (SNDR) and the spurious-free dynamic range (SFDR) were 30.12 and 40.23 dB, respectively. The small input capacitance of the sub-ADC enables a power-efficient track-and-hold amplifier (THA), resulting in a power consumption of 56.2 mW under a supply voltage of 0.9 V. The prototype ADC achieves a figure of merit (FoM) of 107.4 fJ/conversion-step at 20 GS/s.

NN-Based 8FSK Demodulator for the Covert Channel.

In this article, a superposition-based covert channel and its demodulator were proposed and examined. As a covert waveform, an 8FSK modulation was selected. The impact of the channel estimation error and resulting imperfect SIC operation (successive interference cancelation) on the covert information demodulation process was considered. Especially for this imperfection, an NN-based demodulator was proposed. The superiority of this solution over the traditional 8FSK correlator-based receiver was examined for various cases, including the hard- and soft-decision detectors. It was proven that, although NN does not provide BER values equal to zero, even for the perfect SIC, it generally overcomes the traditional correlator-based 8FSK demodulator. Simulation results showed that the NN-base demodulator, in the case of additional covert channel coding, provides error-free demodulation, even for four-times greater channel gain error.

A Low-Phase Error Cascode CMOS Variable Gain Amplifier With 180° Phase Control for Phase Array Systems

A comprehensive analysis is derived to understand the mechanism of phase errors in cascode CMOS variable gain amplifiers (VGAs). According to the analysis, source–drain parasitic capacitors ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$C_{\mathrm {ds}}$ </tex-math></inline-formula> ) of common gate (CG) transistors in off-region are the main causes for phase errors. An independent cascode current canceling (ICCC) VGA is proposed to relax phase errors by minimizing the effect of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$C_{\mathrm {ds}}$ </tex-math></inline-formula> within a broadband. The proposed VGA achieves a 16-dB gain control with a 1.6° phase error and a 0.2-dB gain error from 15 to 25 GHz by 40-nm CMOS technology. Owing to the cascode structure, the peak gain of the VGA is 12 dB with only one stage including input–output pads consuming 16-mW power from 1.1-V voltage. Besides, the VGA can also serve as a 180° phase shifter (PS) due to ICCC structure with a 1.5° phase error and a 0.2-dB gain error from 15 to 25 GHz. The measured −3-dB bandwidth is 5 GHz, and output 1-dB compression point (OP1dB) is over 2.5 dBm in the maximum gain state. The core area is 0.065 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> excluding input–output pads.