Gain Control Technique Research Articles

Multiband LTE-A and 4-PAM Signals Over Large-Core Plastic Fibers for In-Home Networks

This letter presents the transmission of eight standard compliant 64-QAM long term evolution advanced (LTE-A) bands and 1.4 Gb/s 4-pulse amplitude modulation (PAM) signals over 20 m of 1 mm core diameter graded-index polymethyl methacrylate plastic optical fiber. The optical transceiver consists of a red light VCSEL and a p-i-n photodiode followed by a transimpedance amplifier. The LTE-A signals were transparently transmitted with the radio-over-fiber technique and without complex frequency conversion at the receiver side. A gain control technique in the digital domain was used to avoid entering the VCSEL saturation regime. Digital filtering was employed at the transmitter and receiver sides to improve the spectrum shaping of the 4-PAM and LTE-A signals. The proposed system offers a single infrastructure in-home solution capable of accommodating wired services as well as multiband LTE-A wireless services. Only low-cost components were considered in this letter in order to provide a reliable and inexpensive solution for high-capacity in-home networks.

A linear and wide dynamic range transimpedance amplifier with adaptive gain control technique

A linear and wide dynamic range transimpedance amplifier (TIA) for the pulsed time-of-flight imaging LADAR application has been designed and simulated in a 0.18 μm 3.3 V CMOS technology. Specific design techniques, including adaptive gain control technique to widen linear dynamic range, pseudo-differential structure of the front end to decrease the common-mode noise and noise minimization to improve SNR, have been proposed to achieve challenging designs goals with linear dynamic range of 5000:1, high transimpedance gain of 89 dB Ω, bandwidth up to 150 MHz, equivalent input-referred noise current less than 8 $${\text{pA}}/\sqrt {\text{Hz}}$$pA/Hz, in 2 pF photodiode parasitic capacitance. The proposed TIA consumes 165 mW with 3.3 V power supply.

Fractional Gain Control Technique for a Low-Jitter and Area-Efficient Digital Phase-Locked Loop

This paper presents a fractional gain-control technique for a digitally controlled oscillator (DCO). The proposed fine-fractional gain-control scheme improves the jitter performance by suppressing the nonlinear effect of a bang-bang digital phase-locked loop (BB-DPLL). In addition, the proposed structure significantly reduces the chip area, because the proposed fractional DCO dithering circuit requires only one accumulator with an N-2-bit width, while conventional topologies require multiple accumulators with N-bit widths. The simulation result shows that the period jitter of the proposed structure (0.83 ps) is three times better than that of a digital PLL based on a conventional second-order sigma-delta modulator (2.58 ps).

A Bang Bang Phase-Locked Loop Using Automatic Loop Gain Control and Loop Latency Reduction Techniques

This paper presents a digital bang–bang phase-locked loop (DBPLL) that employs automatic loop gain control and loop latency reduction techniques to enhance the jitter performance. Due to noise filtering properties, a DBPLL has an optimal loop gain which gives rise to the best jitter performance, taking into account external and internal noise sources. By using the automatic loop gain control technique, the DBPLL can automatically attain this loop gain in background to minimize the jitter. This paper also exploits time-series analysis to analyze the DBPLL. In particular, the closed-form gain of a bang–bang phase detector (BBPD) is first derived, taking into account reference clock noise and oscillator noise simultaneously. The chip was fabricated in a 40 nm CMOS process. This DBPLL achieves $ fs integrated rms jitter and $ dBc reference spurs. It consumes 3.8 mW from a 1.1 V supply while operating at 3.96 GHz. This translates to an figure-of-merit (FOM) of $- 245$ dB.

Design Techniques for a 60 Gb/s 173 mW Wireline Receiver Frontend in 65 nm CMOS Technology

Design techniques for a complete 60 Gb/s receiver frontend with equalization, output slicing/demultiplexing, and clocking capabilities are described. Current integration combined with a cascode gate-voltage bias gain-control technique enables energy-efficient implementation of CTLE, FFE, and DFE circuits while operating near the speed limits of the technology. Despite following the DFE that has already in principle sliced the data, adaptive error-sampling requires high gain to resolve small residual error signals-this challenge is addressed by the addition of interleaved, offset-canceled deserializing samplers. Clock generation as well as distribution circuits are implemented to complete the receiver frontend. The proposed 65 nm CMOS receiver operates at 60 Gb/s, consuming 173 mW from 1.2 V and 1.0 V supplies.

Voltage lowering and gain control techniques for a single-supply-driven 0.7 V amplifier

A CMOS amplifier architecture is presented with a voltage lowering technique so that it can be driven from a single 0.7 V bias supply. The topology does not need scaled gate voltages (or additional bias circuits) and uses branching of its bias path to reduce power requirement. A three-stage cascaded structure is adopted for high gain with the output common-drain block realizing a gain control mechanism. The technique achieves 6 dB gain regulation (with a control voltage) at the expense of small additional power (1.27 mW). A K-band architecture is simulated with a 90-nm CMOS process to verify the proposed mechanisms. The low-power (7.37 mW) unregulated front-end achieves 27 dB gain with a noise figure range of 2.99–3.06 dB within the 20.5–22.2 GHz bandwidth. Port reflection loss figures ( and ) are analysed to be −8 dB and −11 dB. The circuit has an area requirement of 0.62 mm2 and performs better in terms of power supply requirement and potential packaging cost when compared with simulated results of published millimetre-wave amplifiers.

A 35-mW 30-dB Gain Control Range Current Mode Linear-in-Decibel Programmable Gain Amplifier With Bandwidth Enhancement

This paper presents the design of a programmable gain amplifier (PGA) that serves as an interface between the receiver front-end and the baseband processor. The proposed PGA design is fabricated in a commercial 0.18- μm SiGe BiCMOS process with a topology consisting of two digitally variable gain amplifiers cascaded by a post amplifier and interconnected by differential wideband matching networks that presents an overall enhanced gain bandwidth product. By using the current mode exponential gain control technique, the proposed design achieves a broad 30-dB linear-in-decibel gain range, a gain-independent output 1-dB compression point better than -10 dBm, input/output return loss better than 13 dB, a ±0.75-dB gain flatness over a multi-decade frequency range from 2.5 MHz to 1.17 GHz, a measured in-band group-delay variation of 30 ps, a 35-mW power consumption, and a 0.25- mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> core die area.

Audio Mixer Algorithm for Enhancing Speech Quality of Multi-party Audio Telephony

The speech quality of multi-party audio telephony between two, three or more participants is decreased by audio volume imbalance, audio volume saturation and noise level increase. To solve this issue, this paper proposes an advanced audio mixing algorithm for software-based multi-point control unit. Our approach is based on the combined voice activity detection and gain control technique that consists of a set of algorithms that classify audio signals, estimate audio volumes, adjust gain factors and mix audio signals of all channels. The proposed audio mixing algorithm is computationally efficient, delivers high-quality speech, and is suitable for use in any practical multi-party audio telephony.

Audio Telecom ADC Featuring Click-Free Gain Control Technique, Dithering Insertion, and Idle Tone Shifting

Applying pulsewidth modulation (PWM) to control the gain in audio codecs for mobile applications leads to several advantages, such as the smooth control of tuning parameters, smaller silicon area, and lower power consumption, as compared with other tuning techniques using programmable gain amplifiers and zero crossing detectors. The PWM has to be embedded into the main signal path, preferably in a closed-loop control scheme, in order to exploit its benefits. However, the insertion of dithering and offset controls in a gain setting loop poses the problem of controlling their effects in all gain conditions. This paper reports a novel technique aimed at solving the associated issues and limitations, and provides the experimental proof of the concept through the implementation of a test-chip design on silicon. In particular, this paper reports the design and experimental results of a delta-sigma analog-to-digital converter featuring a click-free gain control technique, dithering insertion, and idle-tone shifting, which has been implemented in a 40-nm complementary metal-oxide-semiconductor technology for commercial telecom audio codec applications.

A Fully Integrated Adaptive Multiband Multimode Switching-Mode CMOS Power Amplifier

This paper presents a fully integrated adaptive multiband multimode switching-mode power amplifier (SMPA) in CMOS technology. The power amplifier (PA) module, consisting of input matching, driver, output stage, load transformation network (LTN), and auxiliary circuitry, utilizes optimized driving waveforms to increase output power and efficiency of a SWPA. The PA module is packaged in a 32 quad flat no-lead package. Based on the detailed analysis on appropriate driving waveforms, the SMPA is designed to maximize its output power and efficiency with minimum on-chip harmonic terminations. Furthermore, an adaptive gain control technique is proposed to control the SMPA gain at back-off while boosting the power-added efficiency (PAE) using a fully integrated tunable LTN. Employing both techniques concurrently enables us to have a multiband multimode SMPA. Measurements on a PA module designed in 90-nm CMOS and incorporating theses findings result in peak PAE of 43% for an output power of 27.1 dBm, associated with a large-signal gain of 22.1 dB at 1.97 GHz, when the devices are biased at 2.8 V. With the tunable LTN PAE at 4- and 6-dB backoff is 30% and 23%, respectively. To our knowledge, this is the first fully integrated multiband multimode SMPA in CMOS technology.

Localization of distinct reflections in rooms using spherical microphone array eigenbeam processing

This paper presents an experimental and comparative study of several spherical microphone array eigenbeam (EB) processing techniques for localization of early reflections in room acoustic environments, which is a relevant research topic in both audio signal processing and room acoustics. This paper focuses on steered beamformer-based and subspace-based localization techniques implemented in the spherical EB domain, including the plane-wave decomposition, eigenbeam delay and sum, eigenbeam minimum variance distortionless response, eigenbeam multiple signal classification (EB-MUSIC), and eigenbeam estimation of signal parameters via rotational invariance techniques (EB-ESPRIT) methods. The directions of arrival of the original sound source and the associated reflection signals in acoustic environments are estimated from acoustic maps of the rooms, which are obtained using a spherical microphone array. The EB-domain-based frequency smoothing and white noise gain control techniques are derived and employed to improve the performance and robustness of reflection localization. The applicability of the presented methods in practice is confirmed by experiments carried out in real rooms.

Dual-mode gain control for a 1 V CMOS hearing aid device with enhanced accuracy and energy-efficiency

A dual-mode gain control (DMGC) technique is presented for accurate and energy-efficient pre-amplification in the front-end system of a hearing aid chip. Compared with the conventional automatic gain control (AGC) approach, the DMGC approach is characterized by an amplification switching mechanism between the pro-linearity discrete gain setting mode and the energy-efficient AGC mode. Thus, the total harmonic distortion (THD) should be significantly improved without incurring any degradation concerning other performances parameters (e.g. gain, noise and power consumption). In order to further enhance the system power efficiency, a self current-adapting (SCA) circuit design technique is proposed. Such SCA circuits are capable of automatically adjusting the bias current in accordance with the sound level. A prototype chip was designed with a 0.13 μm standard CMOS process and tested with 1 V supply voltage. The measurement results show that, for a typical output level of 500 mVp-p, the THD is somewhere below ?64 dB, achieving approximately ten times reduction compared to the previously reported works. The power consumption of less than 45 μW has also been obtained. In addition, the typical input referred noise is only 2 μVrms and the maximum gain attainable is up to 39 dB.

A gain control and stabilization technique for Silicon Photomultipliers in low-light-level applications around room temperature

An experimental setup in dark condition was established to investigate the temperature and bias voltage dependence of the Multi-Pixel Photon Counter (MPPC), one type of the SiPM developed by Hamamatsu. The dark current of an MPPC near room temperature at a given gain can be approximated by an exponential function of temperature which is similar to the behavior of a negative temperature coefficient (NTC) thermistor. According to these facts, a gain control and stabilization circuit for MPPC is developed by using a programmable current sink with temperature compensation. Detailed design and performance analysis results of the circuit in the temperature range from 5.1°C to 33.3°C will be discussed in this paper.

An RF front-end with an automatic gain control technique for a U/V band CMMB receiver

This paper presents a fully integrated RF front-end with an automatic gain control (AGC) scheme and a digitally controlled radio frequency varied gain amplifier (RFVGA) for a U/V band China Mobile Multimedia Broadcasting (CMMB) direct conversion receiver. The RFVGA provides a gain range of 50 dB with a 1.6 dB step. The adopted AGC strategy could improve immunity to adjacent channel signal, which is of importance for CMMB application. The front-end, composed of a low noise amplifier (LNA), an RFVGA, a mixer and AGC, achieves an input referred 3rd order intercept point (IIP3) of 4.9 dBm with the LNA in low gain mode and the RFVGA in medium gain mode, and a less than 4 dB double side band noise figure with both the LNA and the RFVGA in high gain mode. The proposed RF front-end is fabricated in a 0.35 μm SiGe BiCMOS technology and consumes 25.6 mA from a 3.0 V power supply.

A current mode feed-forward gain control system for a 0.8 V CMOS hearing aid

A current mode feed-forward gain control (CMFGC) technique is presented, which is applied in the front-end system of a hearing aid chip. Compared with conventional automatic gain control (AGC), CMFGC significantly improves the total harmonic distortion (THD) by digital gain control. To attain the digital gain control codes according to the extremely weak output signal from the microphone, a rectifier and a state controller implemented in current mode are proposed. A prototype chip has been designed based on a 0.13 μm standard CMOS process. The measurement results show that the supply voltage can be as low as 0.6 V. And with the 0.8 V supply voltage, the THD is improved and below 0.06% (−64 dB) at the output level of 500 mVp-p, yet the power consumption is limited to 40 μW. In addition, the input referred noise is only 4 μVrms and the maximum gain is maintained at 33 dB.

Investigating the Performance of a Transient-Suppressed EDFA in Optical Packet and Burst-Switched Networks

We describe a series of system measurements investigating the performance of a burst-mode or transient-suppressed (TS)-EDFA, specifically designed to reduce the impact of gain transients in dynamic optical networks. We assess the performance of this TS-EDFA in a variety of network contexts. We compare the performance of the TS-EDFA with conventional amplifiers (C-EDFAs) and show its compatibility with supplementary gain control techniques. Finally, we measure gain-transient accumulation along long links using a recirculating transmission loop and show that, for packet-transmission, the number of hops is limited by accumulated transients for a C-EDFA, but limited by accumulated noise for the TS-EDFA.

A Dynamic Dither Gain Control Technique for Multi-Level Delta-Sigma DACs with Multi-Stage Second Order Dynamic Element Matching

A dynamic dither gain control technique for multi-level delta-sigma Digital-to-Analog Converters (DACs) using multi-stage Dynamic Element Matching (DEM) with a second order loop filter is proposed. The proposed technique provides improvement on the mismatch shaping performance through dynamic control of delta-sigma modulator dither gain. A large dither gain, which suppresses DEM operation dependency on input signal, is applied to delta-sigma modulator, when DEM loop filter output is greater than a designed reference. The design example using the proposed technique on a third order 17-level delta-sigma modulator with 3-stage cascaded DEM is shown in this paper. Simulation result with 1% analog segment mismatch shows over 10dB improvement of THD+N performance under -50dB amplitude input signal, compared to the case without the proposed technique.

High-Gain Adaptive Control: A Derivative-Based Approach

In this work, we propose an adaptive scheme which is a counterpart of existing high gain control techniques based on control Lyapunov functions. Given a control Lyapunov function, the main idea is that of tuning the feedback gain according to a suitably-chosen Lyapunov time-derivative. The control gain is not monotonically non-decreasing as in existing techniques, but it is increased or decreased depending on the imposed derivative, thus avoiding the well-known issue of actuator over-exploitation. We are able to show robust convergence of the proposed adaptive control scheme as well as other interesting properties. For instance, it is possible to guarantee an a-priori given upper bound for the transient mode of behavior during adaptation. Furthermore, if the control Lyapunov function is designed based on an optimal control problem, then the control action is nominally optimal, precisely it yields the optimal trajectory for any initial condition, if the actual plant matches the nominal system.

A Study on Performance Enhancement of Packet Detection in MB-OFDM UWB Systems

This paper presents a high performance and hardware efficient packet detection structure, which employs a cross correlator for the M-sample time delayed correlation operation and a signal power calculator using the received input samples less than or equal to a zero-padded suffix of length M. We investigate the detailed characteristics of the proposed packet detector. In this paper, the performance of a class of packet detection algorithms in the ultra-wideband (UWB) channel environments is also studied. The best packet detection algorithm for the multi-band orthogonal frequency division multiplexing (MB-OFDM) UWB transmission is determined through analysis and extensive simulations. The results of analysis show that the proposed packet detection structure has advantages in the hardware complexity as well as performance when compared with the existing packet detection structures. In order to effectively conduct the packet detection before the automatic gain control (AGC) mode, we investigate the effects of both a frequency offset and the initial gain level of a variable gain amplifier (VGA) on the performance of the packet detection. We also suggest a VGA gain control technique to enhance the performance of packet detection.

SOA-Based WDM Metro Ring Networks With Link Control Technologies

We experimentally study the performance of wavelength-division-multiplexing (WDM) metro/access ring networks, based on semiconductor optical amplifiers (SOAs), considering several gain control techniques. We show that gain control through link-control (LC) channel or amplified spontaneous emission (ASE) power recirculation, effectively used in erbium-doped fiber amplifier-based WDM ring networks, introduces serious penalties due to intensity noise transfer, and cannot be used in short-span SOA-based WDM rings. On the other hand, we observe a net benefit using LC channel and ASE extraction for short span rings and a limited WDM channel number, compared with linear operating conditions. An effective optical signal-to-noise ratio improvement of 2.1 dB has been achieved with LC channel extraction with respect to linear operation, for a 4 x 13.5 dB span ring with eight WDM channels. For spans longer than 15 dB, system performance in gain-controlled rings is found to be similar to noncontrolled ones.