Abstract
This paper presents the design of a programmable gain amplifier (PGA) that serves as an interface between the receiver front-end and the baseband processor. The proposed PGA design is fabricated in a commercial 0.18- μm SiGe BiCMOS process with a topology consisting of two digitally variable gain amplifiers cascaded by a post amplifier and interconnected by differential wideband matching networks that presents an overall enhanced gain bandwidth product. By using the current mode exponential gain control technique, the proposed design achieves a broad 30-dB linear-in-decibel gain range, a gain-independent output 1-dB compression point better than -10 dBm, input/output return loss better than 13 dB, a ±0.75-dB gain flatness over a multi-decade frequency range from 2.5 MHz to 1.17 GHz, a measured in-band group-delay variation of 30 ps, a 35-mW power consumption, and a 0.25- mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> core die area.
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