Fractional Gain Control Technique for a Low-Jitter and Area-Efficient Digital Phase-Locked Loop

Abstract

This paper presents a fractional gain-control technique for a digitally controlled oscillator (DCO). The proposed fine-fractional gain-control scheme improves the jitter performance by suppressing the nonlinear effect of a bang-bang digital phase-locked loop (BB-DPLL). In addition, the proposed structure significantly reduces the chip area, because the proposed fractional DCO dithering circuit requires only one accumulator with an N-2-bit width, while conventional topologies require multiple accumulators with N-bit widths. The simulation result shows that the period jitter of the proposed structure (0.83 ps) is three times better than that of a digital PLL based on a conventional second-order sigma-delta modulator (2.58 ps).