GaAs Integrated Circuits Research Articles

Design and implementation of CMOS millimeter-wave ICs and 4096 TX/4096 RX very-large-scale integrated phased-array antenna

The large-scale phased-array system is the key technology for enabling far-distance wireless transmission at millimeter-wave (mm-Wave) frequencies. Traditional mm-Wave phased-array systems are usually implemented using compound semiconductor technology. It is expensive and difficult to realize the system-on-chip (SOC), which greatly limits the applications of traditional phased-array systems. In this paper, the design and implementation of mm-Wave phased-array integrated circuits (ICs) in bulk CMOS and 4096-element transmitter and receiver very-large-scale phased arrays are reported. Although the CMOS technology has the advantages of high integration and low cost, it exhibits a series of technical bottlenecks such as low active gain and high passive loss at mm-Wave frequencies and relatively large performance deviations across temperature. To overcome the intrinsic weakness of CMOS technology, several techniques have been proposed to enhance the performance of mm-Wave phased-array ICs, including the current-reuse g$_{m}$-boost low-noise amplifier, high-efficiency power amplifier using a new layout structure, vector-modulated digital-controlled passive phase shifter, ultra-broadband attenuator with capacitive compensation, compact power divider, and temperature adaptive biasing circuits. Fabricated in 65 nm bulk CMOS, the proposed Ka-band phased-array ICs achieve 3.0 dB noise figure, $15%$ PAE, and accurate amplitude and phase controls without calibration. The CMOS ICs outperform GaAs ICs in terms of integration and cost. Measurement results show that the key performance metrics (e.g., noise figure) of this work are close to that of GaAs ICs. Based on the proposed CMOS phased-array ICs, the design of 1024 TX/1024 RX large-scale integrated phased-array antennas is realized in PCB technology, which are further extended to the scale of 4096 TX/4096 RX phased-array antennas. Finally, vehicle-mounted and shipboard tests are performed using the proposed low-cost and high-integration phased-array antenna terminal for broadband satellite communications.

Integration of a K-Band Receiver Front-End Using a Copper Core Printed Circuit Board

Abstract Increasing demand for high bandwidth wireless satellite connections and telecommunications has resulted in interest in steerable antenna arrays in the GHz frequency range. These applications require cost-effective integration technologies for high frequency and high power integrated circuits (ICs) using GaAs, for example. In this paper, an integration platform is proposed, that enables GaAs ICs to be directly placed on a copper core inside cavities of a high frequency laminate for optimal cooling purposes. The platform is used to integrate a K-Band receiver front-end, composed of four GaAs ICs, with linear IF output power for input powers above −40dBm and a temperature of 42°C during operation.

Solid-source molecular-beam epitaxy for monolithic integration of laser emitters and photodetectors on GaAs chips

A solid-source molecular beam epitaxy has been used to grow Al-free InGaP/GaAs/InGaAs in-plane side emitting laser (IPSELs) devices on foundry available GaAs integrated circuits (IC) chips with integrated metal–semiconductor–metal photodetectors. The GaAs IC chips were cleaned at low temperature (470 °C) by monoatomic hydrogen prior to epitaxy. Br2 reactive ion etching was used after growth to make laser facets and parabolic mirrors for vertical emission. Using these techniques, we obtained laser emission from the integrated IPSEL devices, suggesting that these devices may be an alternative approach to that offered by vertical cavity surface emitting lasers in the fabrication of optoelectronic integrated devices.

Single-event phenomena in GaAs devices and circuits

The single-event upset (SEU) characteristics of GaAs devices and circuits are reviewed. GaAs FET-based integrated circuits (ICs) are susceptible to upsets from both cosmic-ray heavy ions and protons trapped in the Earth's radiation belts. The origin of the SEU sensitivity of GaAs ICs is discussed in terms of both device-level and circuit-level considerations. At the device level, efficient charge-enhancement mechanisms through which more charge can be collected than is deposited by the ion have a significant negative impact on the SEU characteristics of GaAs ICs. At the circuit level, different GaAs digital logic topologies exhibit different levels of sensitivity to SEU because of variations in parameters, including logic levels, capacitances, and the degree of gate or peripheral isolation. The operational and SEU characteristics of several different GaAs logic families are discussed. Recent advances in materials and processing that provide possible solutions to the SEU problem are addressed.

Transmission electron microscopy specimen preparation technique using focused ion beam fabrication: Application to GaAs metal–semiconductor field effect transistors

A specimen preparation technique using a focused ion beam to generate cross-sectional transmission electron microscopy (TEM) samples of GaAs integrated circuits (ICs) was studied. Using a two axes tilting technique it was possible to prepare sample with minimal thickness (∼10 nm) to enhance spatial resolution in TEM and x-ray spectrometer analysis. This method was applied for failure analysis of degraded GaAs ICs. The interfacial microstructure between the gate metallization and the GaAs substrate, caused by high temperature operation, was also investigated

Precision comparison of surface temperature measurement techniques for GaAs ICs

Surface temperature measurement technology for GaAs integrated circuits (ICs) is considered. The three predominant techniques are examined and their precision compared quantitatively. Although infrared microscopy is found to be more imprecise than was previously believed, a measurement procedure with high accuracy based on the diode drop technique (an electrical method) and the transition point technique (a liquid crystal method) is established. The latter has been determined to have a precision as great as +or-2 degrees C for measuring the actual hot spot of nonsealed GaAs ICs. The former is the only method which is useful for sealed ICs. Although it cannot provide actual hot spot information, an accurate temperature with at most +or-1 degrees C error has been obtained at 15 mu m from the spot by utilizing small (3.0 mu m by 1.5 mu m) diodes.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

GaAs Integrated Circuit Manufacturing

In the mid 1980s, reports of exciting progress from GaAs integrated circuit (IC) performance from R&amp;D laboratories world-wide portrayed a rosy future for GaAs. Now, in the early 1990s, true to their reputation, GaAs ICs are still largely the stuff of the future. In fact, deployment of GaAs ICs in real systems has been disappointingly slow. In 1985, the commercial GaAs IC market was forecast to reach $800 million by 1990. The actual figure was only $142 million. To put this number in perspective, it represents less than 0.4% of the total Si IC merchant market.In a recent survey of the GaAs industry, Kato explored the causes for GaAs troubles, with startling findings. The issue certainly does not seem to be a performance one because GaAs ICs are sufficiently ahead of alternative technologies. Material quality is not a problem either. Extremely high-quality 3 in. and 4 in. GaAs wafers are now on the market at reasonable prices. On the other hand, several serious deficiencies center around IC manufacturing. The price of the final GaAs ICs is perceived as not competitive with alternative technologies. This is rooted in the low yields and poor repeatability of the manufacturing lines. A great contribution to cost is time-consuming functionality testing, particularly for analog products. For MMICs (monolithic microwave integrated circuits) in particular, final testing can easily become the bottleneck of the entire fabrication process. There is also much uncertainty about reliability. This might explain to a large extent the low customer confidence in the technology. Kato reports that fundamental technical problems in making GaAs ICs are still believed to remain.

A Simulation Model for Schottky Diodes in GaAs Integrated Circuits

A circuit simulation model for Schottky-barrier diodes is presented which accurately reproduces the diode's forward I-V characteristics. This is achieved by the inclusion of the nonlinear (current-dependent) series resistance typically observed in planar Schottky-barrier diodes. The diode model is targeted for large-signal transient and dc bias analysis where precise solutions are required. Noteworthy features of the model are (a) an easily determined parameter set from either direct measurements or geometrical and process data, (b) requires only one additional node over the constant-resistance diode models, and (c) is applicable to a wide variety of diode geometries. Finally, an example is given to demonstrate the accuracy of the diode model.

Proton isolation for GaAs integrated circuits

Significant improvement in the electrical isolation of closely spaced GaAs integrated circuit (IC) devices has been achieved with proton implantation. Isolation voltages have been increased by a factor of four in comparison to a selective implant process. In addition, the tendency of negatively biased ohmic contacts to reduce the current flow in neighboring MESFET's (backgating) has been reduced by at least a factor of three. The GaAs IC compatible process includes implantation of protons through the SiO 2 field oxide and a three-layered dielectric-Au mask which is definable to 3-µm linewidths and is easily removed. High temperature storage tests have demonstrated that proton isolation, with lifetimes on the order of 106h at 290°C, is not a lifetime limiting component in a GaAs IC process.

Proton Isolation for GaAs Integrated Circuits

Significant improvement in the electrical isolation of closely spaced GaAs integrated circuit (IC) devices has been achieved with proton implantation. Isolation voltages have been increased by a factor of four in comparison to a selective implant process. In addition, the tendency of negatively based ohmic contacts to reduce the current flow in neighboring MESFET's (backgating) has been reduced by at least a factor of three. The GaAs IC compatible process includes implantation of protons through the SiO/sub 2/ field oxide layer and a three-layered dielectric- Au mask which is definable to 3-µm linewidths and is easily removed. High temperature storage tests have demonstrated that proton isolation, with lifetimes on the order of 10/sup 5/ h at 290° C, is not a lifetime limiting component in a GaAs IC process.

Saturated Resistor Load for GaAs Integrated Circuits

Saturated resistors, two-terminal load devices, have been fabricated and evaluated as pull-up loads for GaAs digital integrated circuits. The saturated resistor loads exhibit superior device characteristics compared with FET active loads. Up to 100-percent improvement in the uniformity of the saturation current has been obtained. Ring oscillators with saturated resistor pull-up loads have shown ~20-percent lower speed-power products than ring oscillators with FET active loads. This superior circuit performance is attributed to 1) no gate capacitance, and 2) less backgating effect. Reliability studies using accelerated aging have shown that circuits are more reliable when saturated resistor loads are used.

Gaas Integrated Circuits And Charge-Coupled Devices For High Speed Signal Processing

The superior electronic properties of GaAs, as compared with silicon, make possible the achievement of much higher performance levels in GaAs signal processing devices than have been demonstrated with silicon. Only recently, however, have advances in GaAs materials and processing technology made possible the fabrication of such devices as sub-100 ps propagation delay, high density planar GaAs in-tegrated circuits with large-scale integration (LSI) compatible power levels,1 and high transfer efficiency GaAs charge-coupled devices2 which should be capable of multi-gigahertz clocking rate operation. These high performance device technologies should have major impact on the high speed signal processing area, making possible, through their much higher speeds and lower power requirements, system approaches which could not be practically realized with existing silicon technology. In this paper the advantages of GaAs for high speed signal processing are reviewed and laboratory results obtained with high speed GaAs devices are reported.

LSI processing technology for planar GaAs integrated circuits

A planar GaAs integrated circuit (IC) fabrication technology capable of LSI complexity has been developed. The circuit and fabrication approaches were chosen to satisfy LSI requirements for high yield, high density, and low power. This technology utilizes Schottky-diode FET logic (SDFL) incorporating both high-speed switching diodes and 1-µ m GaAs MESFET's. Circuits are fabricated directly on semi-insulating GaAs using multiple localized implantations. Rapid progress in the development of this technology has already led to the successful demonstration of high-speed ( \tau_{d} \sim 100 ps) low-power (∼500 µW/gate) GaAs MSI (∼60-100 gates) circuits. Extension of the current MSI technology to the LSI/VLSI domain will depend critically on device yield which will be dictated by the GaAs material properties and by the fabrication processes used. The purpose of this paper is to describe a GaAs IC process technology which combines advanced planar device and multilevel interconnect structures with several LSI compatible processes including multiple localized ion implantations, reduction photolithography, plasma etching, reactive ion etching, and ion milling.