GaAs MOSFET Research Articles

A temperature dependent analytical model & performance evaluation of triple-material dielectric-pocket gate-all-around MOSFET

In current article, an analytical model of a Triple-Material Dielectric-Pocket Gate-All-Around (TM-DP-GAA) MOSFET has been presented for elevated temperature conditions. The numerical model of surface potential has been developed for temperatures ranging from 300 to 700 K. The influence of temperature on the drain current, threshold voltage and subthreshold swing has been investigated. The performance of GAA MOSFET and TM-DP-GAA MOSFET has been compared for 30 nm channel length. The TM-DP-GAA MOSFET exhibits lower subthreshold swing, higher transconductance, high drain current and reduced leakage current in comparison to the other semiconductor devices. It has also been noticed that with increasing temperature, the variation in subthreshold current and subthreshold swing is minimal. The subthreshold swing improves by 12.42% over the DPGAA MOSFET. The dielectric pocket-based MOSFET is more resistant to temperature variation.The device simulation is performed using Silvaco TCAD.

Formation of Source/Drain Structures Using Nanosecond Laser Annealing for Multichannel GAA Mosfet Devices

As metal-oxide-semiconductor field-effect transistors (MOSFETs) devices approach their dimensional scaling limits, 3D structures such as gate-all-around FETs (GAAFETs) have been introduced to improve the electrical characteristics of transistors by increasing the effective channel width. In modern logic devices with a GAA structure, in-situ doped epitaxial silicon is grown on recessed source/drain (S/D) regions using selective epitaxial growth (SEG) process. However, the SEG process poses a competitive disadvantage in terms of complexity and cost. To simplify the integration process, we propose a method for forming S/D without relying on SEG. In this study, we investigate the formation of S/D using nanosecond laser annealing process in devices with multilayer channels. Three pairs of Si/Si0.7Ge0.3 multilayer films were deposited on Si (100) substrates using ultra-high vacuum chemical vapor deposition (UHVCVD). After deposition, boron and phosphorus dopants were implanted into the structure. Samples were then subjected to nanosecond laser annealing under various conditions using a krypton fluoride (KrF) pulse laser. Finally, we obtained recrystallized and doped films that function as S/D. Transmission electron microscopy (TEM) confirmed the microstructure of recrystallized films as function of increasing laser power density. Additionally, the dopant distribution was analyzed using secondary ion mass spectrometry (SIMS). High resolution X-ray diffraction (HR-XRD) was employed to examine the strain behavior in the films. Results indicate that the nanosecond laser annealing process is a viable method for forming S/D in devices with Si/SiGe multilayer channels. Acknowledgements This work was supported by the Joint Program for Samsung Electronics at Yonsei University and the Technology Innovation Program (20010598) funded by the Ministry of Trade, Industry & Energy (MOTIE).

Electrical characteristics of Si0.7Ge0.3/Si heterostructure-based n-type GAA MOSFETs

Electrical characteristics of Si0.7Ge0.3/Si heterostructure-based n-type GAA MOSFETs

Comparative analysis of heavy ions and alpha particles impact on gate-all-around TFETs and gate-all-around MOSFETs

Comparative analysis of heavy ions and alpha particles impact on gate-all-around TFETs and gate-all-around MOSFETs

Exploration of Linearity Analysis in Nanotube GAA MOSFET Through Simulation-Based Study Utilizing Multi-Material Gate Technique

Exploration of Linearity Analysis in Nanotube GAA MOSFET Through Simulation-Based Study Utilizing Multi-Material Gate Technique

Impact of Process-Induced Inclined Side-Walls on Gate Leakage Current of Nanowire GAA MOSFETs

Impact of Process-Induced Inclined Side-Walls on Gate Leakage Current of Nanowire GAA MOSFETs

GaAs MOSFETs with in situ Y2O3 dielectric: attainment of nearly thermally limited subthreshold slope and enhanced drain current via accumulation

Planar GaAs(100) depletion-mode (D-mode) MOSFETs as passivated with in situ deposited Al2O3/Y2O3 dielectric have shown enhancement of the drain current by 167% and 333% as the gate voltage (V g) increased from flat-band voltage (V fb), namely V g = V fb = 0.5 V to V g = 2 V and V g = 4 V, respectively, much higher than those in the previously published GaAs-based D-mode MOSFETs. In addition, we have achieved a high I on/I off of 107 and a subthreshold slope (SS) of 63 mV dec−1, which approaches the thermal limit of 60 mV dec−1 at 300 K and is the record-low value among planar (In)GaAs MOSFETs. Moreover, using the measured SS data, we have deduced an interfacial trap density (D it) of 4.1 × 1011 eV−1 cm−2 from our Al2O3/Y2O3/GaAs MOSFET, the lowest value among the planar (In)GaAs MOSFETs.

Design and Comparative Analysis of Silicon and GaAs MOSFET for Low Power Applications

The demand for low power consumption in modern electronic devices has led to the development of various technologies, including usage of different materials such as Si and GaAs. In this paper, we present a design and comparative analysis of Si and GaAs MOSFETs for low power applications. The analysis includes the electrical characteristics, performance parameters, and power consumption of both devices. The Si MOSFET and GaAs MOSFET are simulated and analyzed using TCAD tools, and the results are compared. The simulation results show that the GaAs MOSFET has a higher transconductance (gm) compared to the Si MOSFET. However, the Si MOSFET has a lower gate leakage current (Ig) and lower power consumption at low operating frequencies. We also investigate the effect of scaling on the performance and power consumption of both MOSFETs. The results show that scaling improves the performance of both devices, but the power consumption increases as the device dimensions are reduced. The comparative analysis of Si and GaAs MOSFETs for low power applications provides useful insights into the selection of suitable MOSFET technology for specific applications. The results show that both Si and GaAs MOSFETs have their advantages and disadvantages, and the choice depends on the application requirements.

Noise and linearity analysis of recessed-source/drain junctionless Gate All Around (Re-S/D-JL-GAA) MOSFETs for communication systems

Noise and linearity analysis of recessed-source/drain junctionless Gate All Around (Re-S/D-JL-GAA) MOSFETs for communication systems

Enhancement of Thermal Characteristics and On-Current in GAA MOSFET by Utilizing Al2O3-Based Dual-κ Spacer Structure

By utilizing the dual- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\kappa $ </tex-math></inline-formula> spacer (DS) technique, a novel structure has been proposed to improve the thermal characteristics and ON-current ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{ \mathrm{\scriptscriptstyle ON}}{)}$ </tex-math></inline-formula> in gate-all-around (GAA) MOSFETs. The proposed GAA MOSFET structure utilizes DS, which contains aluminum oxide (Al2O3) as an inner spacer so that the self-heating effect (SHE) could be improved from the high thermal conductivity of Al2O3. To verify the proposed device structure, 3-D technology computer-aided design (TCAD) simulation has been performed through Synopsys Sentaurus tool. As a result, when the DS structure and Al2O3 are utilized in GAA MOSFET, the maximum lattice temperature ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${T}_{\text {max}}{)}$ </tex-math></inline-formula> is improved from 628 to 509 K, and the thermal resistance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\text {th}}{)}$ </tex-math></inline-formula> is improved by 49%. According to this thermal improvement, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{ \mathrm{\scriptscriptstyle ON}}$ </tex-math></inline-formula> and OFF-current ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{ \mathrm{\scriptscriptstyle OFF}}{)}$ </tex-math></inline-formula> are also simultaneously improved in the proposed GAA MOSFET. Furthermore, since Al2O3 has lower permittivity than HfO2, the gate capacitance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C}_{\text {gate}}{)}$ </tex-math></inline-formula> could also be improved in the proposed GAA MOSFET. In essence, the proposed GAA MOSFET structure utilizes high thermal conductivity and low permittivity of Al2O3 with DS structure.

A New Approach to Modeling Ultrashort Channel Ballistic Nanowire GAA MOSFETs.

We propose a numerical compact model for describing the drain current in ballistic mode by using an expression to represent the transmission coefficients for all operating regions. This model is based on our previous study of an analytic compact model for the subthreshold region in which the DIBL and source-to-drain tunneling effects were both taken into account. This paper introduces an approach to establishing the smoothing function for expressing the critical parameters in the model’s overall operating regions. The resulting compact model was tested in a TCAD NEGF simulation, demonstrating good consistency.

A Junctionless Single Transistor Neuron With Vertically Stacked Multiple Nanowires for Highly Scalable Neuromorphic Hardware

A junctionless single-transistor neuron (JT-neuron) composed of vertically stacked multiple nanowires (NWs) with a gate-all-around structure (GAA) is demonstrated to drive more synapses compared with a single NW junctionless GAA MOSFET for neuromorphic hardware. A homogeneously doped junctionless structure is advantageous for fabrication simplicity compared with a heterogeneously doped junction structure, which has been widely used as an inversion mode transistor. The nature of the junctionless MOSFET is robust to punchthrough or drain-induced barrier lowering (DIBL) in a scaled transistor. Furthermore, vertically stacked multiple NWs are favorable for improving the ON-state current to be able to derive more synapses and higher packing density without sacrifice of the footprint area compared with a laterally deployed NW structure. To evaluate the feasibility of applying the JT-neuron to a spiking neural network (SNN), experimental-based simulations are performed. A recognition accuracy of 91.7% is achieved for Modified National Institute of Standards and Technology (MNIST) handwritten digits.

Investigation of Self-Heating Effects in Vertically Stacked GAA MOSFET With Wrap-Around Contact

A contact resistance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{c}$ </tex-math></inline-formula> ) becomes a major parasitic resistance in highly scaled modern semiconductor devices. A wrap-around contact (WAC) has been suggested as a promising solution to reduce the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{c}$ </tex-math></inline-formula> , because its contact area is larger than that for the conventional top contact (TC) structure. Therefore, in this article, the electrical and thermal characteristics are widely investigated in vertically stacked gate-all-around (GAA) MOSFET with a WAC by using a 3-D technology computer-aided design (TCAD) simulation. First, compared with the TC, the WAC shows 1.74 times higher ON-state current. It is attributed in part to the low <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{c}$ </tex-math></inline-formula> and in part to the low source–drain resistance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\text {SD}}$ </tex-math></inline-formula> ). Furthermore, thermal resistance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\text {th}}$ </tex-math></inline-formula> ) is also reduced by 9.73% in WAC, which improves self-heating effects (SHEs). Considering the results, it is expected that the WAC structure could be an attractive candidate to simultaneously improve device performance and reliability.

Subthreshold Modeling of GAA MOSFET Including the Effect of Process-Induced Inclined Sidewalls

The impact of process-induced inclination angle (<inline-formula> <tex-math notation="LaTeX">$\theta $ </tex-math></inline-formula>) of nonvertical sidewalls of the fabricated quadruple gate (QG) metal&#x2013;oxide&#x2013;semiconductor field-effect transistor (MOSFET) on subthreshold characteristics has been analytically modeled and analyzed using the equivalent width, equivalent oxide, and coupling between the two equivalent double gate (DG) MOSFETs. A quasi-3-D scaling length model has been formulated accounting <inline-formula> <tex-math notation="LaTeX">$\theta $ </tex-math></inline-formula> and corner gates, which was subsequently applied to derive the channel center potential, threshold voltage, subthreshold current, subthreshold swing (SS), and noise margin (NM) for subthreshold logic applications of trapezoidal (Tz) gate-all-around (GAA) MOSFETs. The newly formulated models were successfully verified using TCAD calibrated to the experimental results of our fabricated QG-MOSFETs. We found that for channel length, <inline-formula> <tex-math notation="LaTeX">${L}_{g}$ </tex-math></inline-formula> &#x003D; 50 nm, Fin height, <inline-formula> <tex-math notation="LaTeX">${H}_{Fin}$ </tex-math></inline-formula> &#x003D; 20 nm, and Fin top width, <inline-formula> <tex-math notation="LaTeX">${W}_{top}$ </tex-math></inline-formula> &#x003D; 10 nm, the potential barrier of TzGAA MOSFET falls by 4.7&#x0025; at <inline-formula> <tex-math notation="LaTeX">$\theta =30^\circ $ </tex-math></inline-formula> compared to rectangular cross section, thereby, deteriorating the short-channel immunity of the device. The SS roll-up, threshold voltage roll-off, drain induced barrier lowering (DIBL), voltage transfer curve (VTC) of subthreshold CMOS inverter, and NM degradation due to inclined sidewalls have been calculated using the developed models. According to the scaling theory, the minimum <inline-formula> <tex-math notation="LaTeX">${L}_{g}$ </tex-math></inline-formula> for a NM degradation of 5 mV is 30.5 nm corresponding to <inline-formula> <tex-math notation="LaTeX">$\theta =0^\circ $ </tex-math></inline-formula>, and 42.7 nm at <inline-formula> <tex-math notation="LaTeX">$\theta $ </tex-math></inline-formula> &#x003D; 30&#x00B0; for <inline-formula> <tex-math notation="LaTeX">${H}_{Fin}$ </tex-math></inline-formula> &#x003D; 20 nm.

Development of an analytical model of work function modulated GAA MOSFET for electrostatic performance analysis

This paper describes a continuous and almost linearly modulated work-function adjustment between 4.8–4.2eV using Hf-Mo binary alloy. The work-function modulated (WM) metal gate is applied to a gate all around MOSFET (GAA) for better electrostatic control. The threshold voltage is tuned by linearly modulating the gate metal work function. The threshold voltage extracted for dual-GAA MOSFET is initially 0.705 V. However, introducing work-function modulation, the threshold voltage is shifted to 0.620 V for WMGAA and 0.632 V for dual-WMGAA MOSFET. The simulation results validate the benefits of using work-function modulated metal gate in place of normal metal gate in terms of electron mobility, threshold voltage (Vth), and drain current (Id). An improved device performance with reduced short channel effect shows the capability of this device for various circuit applications.

Extensive Study of Position-Dependent Multi-Channel GAA MOSFET and its Effect on Device Performance

Extensive Study of Position-Dependent Multi-Channel GAA MOSFET and its Effect on Device Performance

Effect of Channel Material on the Performance Parameters of GAA MOSFET

Effect of Channel Material on the Performance Parameters of GAA MOSFET

Total Ionizing Dose Effects on Nanosheet Gate-All-Around MOSFETs Built on Void Embedded Silicon on Insulator Substrate

The total ionizing dose response of nanosheet gate-all-around metal-oxide-semiconductor field effect transistor (NS GAA MOSFET) fabricated on novel void-embedded silicon on insulator (VESOI) substrate was investigated in this work. Strong radiation tolerance with as small as 46.6mV threshold voltage shift and non-discernable increase of off-state current were observed even at a dose of 7Mrad(Si) X-ray irradiation. Both the experiment and simulation results reveal that the radiation tolerance of the MOSFET device can be inherently attributed to the GAA channel. Our work undoubtedly demonstrates that the NS GAA device on VESOI substrate has great potential for radiation-harden applications under heavy radiation environment.

Silicon Nanowire GAA-MOSFET: a Workhorse in Nanotechnology for Future Semiconductor Devices

In today’s world, semiconductor nanowire GAA-MOSFET devices have stimulated a lot of scientific research interest in the field of semiconductor. It has been observed as one of the strong and gifted structure for future generation nano-scaled devices and integrated circuits (ICs). Basically, the term nanotechnology is the key powerhouse of semiconductor device engineering and technology to produce and operate the materials at nano-meter scale (10−9 m or 1 nm) either by top-down approach where the bulk materials are converted to a group of nano particles (atoms) or by bottom-up approach where the single groups of nano particles (atoms) are converted to the bulk materials. Nanowire GAA MOSFET is considered as work horse in semiconductor industry due to great electrostatic controllability over the channel and tight coupling. This review article investigates the different structural designs of nanowire devices using nanotechnology approaches for future device applications.

Gate-All-Around MOSFET Built on Void Embedded Silicon on Insulator Substrate

A novel method for manufacturing gate-all-around metal-oxide-semiconductor field effect transistor (GAA MOSFET) based on void embedded silicon on insulator (VESOI) substrate is demonstrated in this work. VESOI with embedded submicron void chambers has been designed to fabricate suspended silicon channels by a one-step lithography and dry etching process. GAA MOSFET built on VESOI substrate exhibits excellent characteristics with subthreshold swing (SS) about 63mV/dec, ON/OFF ratio of 1010, drain-induced barrier lowering (DIBL) less than 12mV/V and strong tolerance to back gate bias. This method shows significant advantages to fabricate suspended Si channels, and can be readily extended to other types of material systems for low-power and high-performance applications.