Function Of Stress Time Research Articles

Interface defect generation probed by low voltage stress induced leakage current

Conduction behavior of n-MOSFET capacitors with ultra-thin oxides was investigated before and after constant current stress. It was found that stress induced leakage current (SILC) strongly depends on the low sense voltages. Conduction mechanism of the low voltage SILC (LV-SILC) was analyzed systematically, based on the assumption that the LV-SILC is due to interface trap-assisted tunneling process (ITAT). Using the LV-SILC as a probe, generation of interface defects was investigated. Defects at both interfaces of anode and cathode are involved in ITAT process. Defect generation is a nonlinear process. Dependence of defect generation rate as a function of stress time could be used as a detector of oxide breakdown.

Spatial Distribution of Interface Traps in DeMOS Transistors

The spatial distribution of interface traps in a p-type drain extended MOS transistor is experimentally determined by the analysis of variable base-level charge pumping spectra. The evolution of the interface trap distribution can be monitored as a function of the hot-carrier stress time. A double peaked interface trap density distribution, located in the spacer oxide, is extracted. The interface trap density in the poly overlapped drift region is constant as a function of stress time. No channel degradation is observed.

Operating limits for RF power amplifiers at high junction temperatures

LDMOS RF––power amplifier components usually operate under severe conditions challenging long-term reliability. These components are subjected to high power dissipation and consequently high junction temperatures. Failure mechanisms are highly temperature dependent and driven by coupled electro-thermo-mechanical fields as a function of stress time. In this work we have investigated the reliability of such a component. Power cycling was used to assess its reliability by introduction of temperature gradients and transient at elevated junction temperatures. The experimental lifetime acceleration conditions provided transient thermal constraints to the thermo-mechanical strength of the silicon die. Power dissipation has been adjusted to cover a broad temperature range ( T j max : 200–300 °C) in the peak of a single power cycle. Different failure modes have been observed and related to the different temperature ranges. The experimental results have been combined with thermo-mechanical FE-simulations in ANSYS, leading to the validation of simulation models and implementation in a larger simulation network. The power cycling approach as applied in this paper provided a useful addition to the steady state reliability information. In this way, clear information about margins for safe operation under dynamical conditions has been obtained. This information is needed to fully exploit the functional capability of the component and avoid over-specification in the final application. Overall, the LDMOS RF–PA component showed excellent reliability which makes it suitable for application in telecom devices.

Study on the instability of organic field-effect transistors based on fluorinated copper phthalocyanine

The effects of positive and negative gate-bias stress on organic field-effect transistors (OFET) based on tantalum (Ta)/tantalum pentoxide (Ta 2O 5)/fluorinated copper phthalocyanine (F 16CuPc) structure are investigated as a function of stress time and stress temperature. It is shown that gate-bias stress induces a parallel threshold voltage shift (Δ V T) of OFETs without changes of field-effect mobility μ EF and sub-threshold slope (Δ S). The Δ V T is observed to be logarithmically dependent on time at high gate-bias appropriate to OFET operation. More importantly, the shift is directional, namely, be large shift under positive stress and almost do not move under negative stress. The threshold voltage shift is temperature dependent with activation energy of 0.51 eV. We concluded that threshold voltage shift of the OFET with F 16CuPc as active layer is due to charge trapping in the insulator in which trapped carriers have redistribution.

Stability of Advanced Gate Stack Devices

The stability of poly-Si gated (∼1.2 nm equivalent oxide thickness, EOT) and (∼3.1 nm EOT) n-channel metal oxide semiconductor field effect transistor devices were assessed after constant current stressing of the gate. The changes in threshold voltage and transconductance were measured as a function of stress time and stress current over the range of to C of injected charge per square centimeter. With forming gas annealed positive shifts in the threshold voltage exhibited a power- law dependence. Under high stressing conditions, a power-law dependence of degradation of threshold voltage on the injected charge was observed. Stressing at high current was seen to generate traps. Stressing at low current revealed a saturation of the threshold voltage after modest stressing times. Stressing on deuterium annealed sample showed less and shift (under high injection conditions), which is attributed to the effectiveness of heavier in preventing trap generation under high stressing conditions. With stressed at similar electric fields, the threshold voltage shifted negatively and the transconductance increased. © 2004 The Electrochemical Society. All rights reserved.

Charge trapping related threshold voltage instabilities in high permittivity gate dielectric stacks

An experimental and modeling study of charge trapping related threshold voltage shifts in Al2O3 and HfO2 n-type field effect transistors (nFET) is reported. The dependence of threshold voltage, subthreshold slope, and gate leakage currents on stressing time and injected charge carrier density are investigated as a function positive bias stress voltage and temperature. Based on experimental data, a model for trapping of charges in the existing traps is developed. The model is similar to SiO2 charge trapping models with one exception. Unlike SiO2 models, the model assumes a continuous distribution in trapping capture cross sections. The model predicts that threshold voltage would increase with a power law dependence on stressing time and injected charge carrier density (Ninj) in the initial stages of stressing. The model calculates threshold voltage shifts as a function of stress time and Ninj, thereby provides estimates of threshold voltage shifts after 10 years lifetime. It also provides insights into the nature of traps by estimating trapping capture cross sections. The calculated results are shown to be consistent with both Al2O3 and HfO2 data over several decades of stressing time and Ninj. Using the model, a comparison between Al2O3 and HfO2 is made. In addition, the model is compatible with charge trapping data reported by other research groups.

Bias stress in organic thin-film transistors and logic gates

Threshold voltage instabilities of all-organic thin-film transistors are investigated as a function of stress time and stress bias. The dominant effect is a positive threshold shift for negative gate bias stress which is explained by mobile ions drifting in the insulator when a gate field is applied. Trapping of charge carriers at the semiconductor–insulator interface plays only a minor role. Furthermore, we investigate the stress behavior of a basic logic element, an inverter. In comparison to a single transistor, we observe improved stability which arises from partial compensation of the parametric shifts during operation.

Time-dependent breakdown of ultra-thin SiO2 gate dielectrics under pulsed biased stress

Ultra-thin SiO/sub 2/ films (t/sub ox//spl sim/2.0 nm) were stressed under DC, unipolar, and bipolar pulsed bias conditions up to a pulse repetition frequency of 50 kHz. The time-to-breakdown (t/sub BD/), the number of defects at breakdown (N/sub BD/), and the number of defects generated inside the oxide as a function of stress time were monitored during each stress condition. Oxide lifetime under unipolar pulsed bias is similar to that under DC conditions; however lifetime under bipolar pulsed bias is significantly improved and exhibits a dependence on pulse repetition frequency. The observation of a lifetime increase under bipolar pulsed bias for the oxide thickness and voltage range used in this study suggests that a different physical mechanism may be responsible for the lifetime increase from that assumed in earlier studies for thicker films.

Hot-carrier-induced oxide charge trapping and interface trap creation in metal–oxide–semiconductor devices studied by hydrogen/deuterium isotope effect

A method based on the hydrogen/deuterium isotope effect is proposed to separate and quantify the effects of interface trap creation and oxide charge trapping on hot-carrier-induced degradation in n-channel metal–oxide–semiconductor field-effect transistors (MOSFETs). Hydrogenated and deuterated transistors were subjected to hot-carrier stress with a fixed drain voltage Vds and various gate voltages Vgs. The threshold voltage Vt and interface trap density Nit were recorded as a function of stress time. It is found that at low Vgs stress when equal numbers of interface traps are created, the shift of Vt is larger in hydrogenated transistors than in deuterated transistors. Increasing Vgs to 1/3Vds produces no noticeable difference of Vt shift in these two kinds of transistors. However, further increasing Vgs results in larger Vt shift in deuterated transistors than in hydrogenated ones. From a quantitative analysis, the contribution of oxide charge trapping to Vt shift is separated from the contribution of interface trap creation. The results suggest that interface trap creation is the dominant mechanism for hot-carrier-induced degradation in n-channel MOSFETs.

Intrinsic reliability projections for a thin JVD silicon nitride gate dielectric in P-MOSFET

A comprehensive study of the intrinsic reliability of a 1.4-nm (equivalent oxide thickness) JVD Si/sub 3/N/sub 4/ gate dielectric subjected to constant-voltage stress has been conducted. The stress leads to the generation of defects in the dielectric. As a result, the degradation in the threshold voltage, subthreshold swing, gate leakage current, and channel mobility has been observed. The change in each of these parameters as a function of stress time and stress voltage is studied. The data are used to project the drift of a MOSFET incorporating JVD nitride at a low operating voltage of 1.2 V in 10 years. Based on these projections, we conclude that the increase in the Si/sub 3/N/sub 4/ gate dielectric leakage current does not pose a serious threat to device performance. Instead, the degradation in the threshold voltage and channel mobility can become the factor limiting the device reliability.

Optimization of pre-metal Dielectric (PMD) materials

It is very important to select superior interlayer pre-metal dielectric (PMD) materials that can act as a penetration barrier to various impurities created by the chemical mechanical polishing (CMP) process. In this paper, hot carrier degradation and device characteristics were studied on various materials of PMD-1 layers, which included low-pressure tetra-ethyl-ortho-silicate glass (LP-TEOS), Si-rich (SR)-oxide, plasma-enhanced (PE)-oxynitride, PE-nitride and PE-TEOS films. Pressure cooker test (PCT) analysis was used to obtain the electrical characteristics of devices, such as the shifts in threshold voltage and transconductance as a function of stress time, junction leakage current and breakdown voltage of field transistors with variation of these PMD-1 materials. Also, the most effective PMD-1 materials which can prevent degradation effects due to hot carrier stress were investigated. From experimental results, it is clearly shown that silicon oxide turned out to be a better PMD-1 material than both PE-oxynitride and PE-nitride. From the results, it is suggested that LP-TEOS film is the best PMD-1 material among the silicon oxide samples. © 2001 Kluwer Academic Publishers

Bridge-vehicle interaction using extended FE analysis

To describe the behaviour of a bridge with a crossing vehicle (MDOF) using FE analysis, a method is used based on a commercial software package. The connection between a bridge and a vehicle whose location is variable by time can be realized as a Lagrange condition within the equation of variation. The numerical results are used for a discussion of influence parameters representing the roughness of the road surface and of dynamic measurements performed at a bridge. As an example, the calculated dynamic stress time function and the dynamic portion based on a measured strain record are compared.

Compact LDD nMOSFET degradation model

In this paper, we present a compact degraded I-V model for submicron lightly-doped drain (LDD) MOSFET's. The analytical and physics-based model was developed using the drift equation and considering the nonuniform spatial hot-carrier-induced interface states and the detailed LDD structure. It can be used to calculate fresh channel electric field and drain current by turning off the effect of hot-carrier-induced interface states. Using the fresh electric field in conjunction with a simplified energy balance equation, the nonuniform spatial distribution of induced interface states ran be calculated. By incorporating this distribution into the degraded current model, we can describe the damaged I-V characteristics and channel electric fields as a function of stress time. The model includes the effects of series resistances and carrier velocity saturation. It can be used to calculate time-dependent degraded drain current, and is a time-saving CAD model.

Modelling the degradation in the subthreshold characteristics of submicrometre LDD PMOSFETs under hot-carrier stressing

Hot-carrier injection is observed increasingly to degrade the subthreshold characteristics with the scaling of LDD PMOSFETs. A physical subthreshold current model is applied to the fresh and hot-carrier-stressed submicrometre channel length devices. The channel length reduction is subsequently extracted. An empirical relationship is developed to characterize the degradation parameters as a function of stress time and channel length. With the use of this relationship, we can determine the device lifetime or predict the minimum allowable channel length (for a certain percentage of degradation and lifetime) that is applicable for a specific technology. The degradation of the PMOSFET subthreshold current, which imposes a major limit on device reliability for deep-submicron technology and low-power applications, is fully described by a physical analytical model.

A Growth Model of Stress Voids in Integrated Circuit Metallization

ABSTRACTStress voiding is caused by the difference in the thermal expansion coefficients of the metallization lines and the surrounding passivation. Volumes of individual stress voids are measured as a function of stress time at 200°C, 180°C, and 150°C in 1-μm-wide AlCu(1%wt) integrated circuit metallization lines. The time needed for void growth to saturate, and the total void volume depend on the stress temperature. If the void growth is regarded as an isothermal phase transformation in which voids are formed as precipitates at the void nucleation sites, the void volume growth is accurately described by the Avrami equation. Depending on the temperature, the time power n ranges between 0.5 and 1.5. First principle calculations are in excellent agreement with the measurements. The impact of the above results on electromigration testing is discussed.

The curvilinear integral method: Testing 2 (under non-proportional pulsating axial force and internal pressure)

The curvilinear integral method suggests another mathematical point of view on life prediction: it does not consider cycles of loading and damage summation on cycles, nor reduction to some ‘equivalent quantity’, nor a critical plane, but rather loading differentials ds and summation of damage differentials dD on ds by means of a (curvilinear) integral. Thus the stress-time functions σx(t), σy(t), τxy(t) (components of plane stress) are allowed to be arbitrary. From such a mathematical point of view, the well-known S-N fatigue line, to which we are all accustomed after Wöhler, is not the right basis for life prediction under arbitrary stress-time functions; it is only a concrete integral result under cyclic functions (of constant amplitudes). The right basis is searched for behind the integral sign, i.e. at the differential level, as so-called Rr, Rc and Rτ functions. In the present Testing 2, experimental life data by Bhongbhibhat, Dietmann and Schmid under sinusoidal, triangular and trapezoidal wave forms have been used. The data testify for great influence of the wave forms and mainly their mutuality on fatigue life. They could be a touchstone for each life prediction method. The results of Testing 2 are positive for the integral method.

Model for a general mechanical blood damage prediction.

Knowledge of the correlation between mechanical loading of formed blood elements and the amount of their destruction is important for the prediction of blood trauma in artificial circulatory devices as well as in natural circulation. A hemodynamic assessment and optimization of artificial organs to minimize trauma could be undertaken in the design phase given a comprehensive mechanical blood damage model. A theory to determine blood trauma theoretically as a combination of a mechanical loading analysis and a phenomenological blood damage resistance hypothesis is presented. Arbitrary stress-time functions of blood particles predicted by flow analysis are reduced to a set of simple time functions for which the damage behavior may, in principle, be obtained from mechanical blood damage tests. A classification of those stress functions into damaging and nondamaging parts is followed by an overall trauma prediction considering cumulative effects by means of a damage accumulation hypothesis. Theoretical determination of blood destruction caused by mechanical stresses in a centrifugal pump is one possible application of the proposed theory. The strategy of hemolysis prediction is demonstrated for the Aries Medical Isoflow Pump. Irregular stress-time loading functions of particles passing the pump domain obtained by three-dimensional numerical flow simulations were reduced and classified into harmonic components. To relate these functions to their hemolytic response can only be done in a qualitative manner since blood damage behavior under transient stress loading has not been sufficiently investigated. Accurate prediction of blood trauma using the proposed theory will require detailed study of the influence of frequency and amplitude of harmonic stress loading on formed blood elements.

The Role of the Si-SiO2 (CVD) Interface in Degradation Effects for High-Speed Bipolar Transistors

AbstractThe intent of the present work is to analyze device degradation and reliability in terms of their microscopic origins. The base-emitter junction of the advanced, “double-poly”, self-aligned bipolar transistor contacts the SiO2 sidewall spacer. During normal circuit operation, the base-emitter junction experiences a reverse bias which as a stress in time degrades the current gain of the transistor. Both a decrease of the gain, as well as an increase in the noise are observed. The forward base current increase as a function of stress time follows △IB ∼ tn. We present evidence that the defects are occurring at the Si-Si02 interface from perimeter to area comparisons. The weak temperature dependence of the forward base current in degraded transistors shows that trap-assisted tunneling current through the Si-SiO2 interface states is involved. The random-telegraph-signals observed for the first time in a silicon bipolar transistor are a direct identification of damage at the Si-SiO2 interface. 2D simulation of the potential and field near the interface allows us to show that damage can be expected.

Suppression of interface-state generation in reoxidized nitrided oxide gate dielectrics

Reoxidized nitrided oxide gate dielectrics are characterized following electrical stress, in order to study the mechanism by which they are able to inhibit interface-state generation, as compared to silicon dioxide. It is found that the energy spectrum of the few interface states which are generated in reoxidized nitrided oxides differs from that of states generated in lightly nitrided oxides or in silicon dioxide. We have also measured interface-state generation as a function of stress time and stress polarity for different dielectrics, and observed two characteristic types of fluence dependencies. Interface states which are generated linearly with fluence are modeled using a simple first-order rate equation, which depends on the density of interface-state precursor sites. A sublinear fluence dependence is successfully modeled by including the effect of interfacial strain relaxation. Based on these results, we argue that the first type of interface-state generation, which follows a linear fluence dependence, is suppressed in electrically-stressed reoxidized nitrided oxides because the interface has fewer defect precursor sites.

Hot carrier induced bipolar transistor degradation due to base dopant compensation by hydrogen: theory and experiment

New experimental and analytical results are presented which show that extrinsic and intrinsic base dopant compensation by hydrogen is responsible for large changes in the bipolar transistor parameters of emitter-base breakdown voltage (V/sub ebo/), forward collector current (I/sub c/) and series base resistance (R/sub bx/) when such transistors are operated under avalanche and inverted mode stress conditions. A new physical model has been developed to explain the observed changes in V/sub ebo/ and I/sub c/ as a function of stress time, and the analytical results are shown to be well correlated with the experimental data. Lastly, the effects of degradation on transistor voltage gain bandwidth (f/sub max/) and emitter coupled bipolar comparator delay (/spl tau//sub delay/) are assessed and discussed in terms of circuit performance degradation. >