Function Of Stress Time Research Articles

Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort

A static timing analysis (STA) methodology based on an effective current source model (ECSM) is proposed for the first time for estimating the aging aware path-level timing performance and its impact on the logical effort of a CMOS inverter for digital timing closure in pre-stress and post-stress conditions. Degradation in the threshold voltage (Vth) of PMOS occurs due to temporal variability mechanisms (aging), such as negative bias temperature instability, resulting in delay degradation of a standard cell. Therefore, we proposed a technique to make the STA process aware of this degradation by developing device-level variation aware (with aging) timing models of CMOS inverters to represent threshold-crossing points (TCPs) in an ECSM.libs file as a function of stress time (t). A device-level approach for Vth degradation into different aging conditions, such as static and dynamic, is developed for a given process design kit to update TCPs in a (.libs) file as a function of t. A python-based tool is being developed to estimate the path-level timing performance of digital circuits in pre-and post-stress conditions. Again, we developed a technique for relating the inverter’s logical effort with t to resize a near-critical path in pre-stress conditions for achieving digital timing closure in pre-and post-stress conditions. The verification and validation of the proposed model with different benchmark circuits are performed using a parasitic extracted netlist in Eldo SPICE environment with 65 nm CMOS process technology. Finally, our model reduces the number of SPICE/Stress simulations by 98.13% compared to the previously reported only simulation-based techniques.

Characterisation of the soft tissue viscous and elastic properties using ultrasound elastography and rheological models: validation and applications in plantar soft tissue assessment

Objective. The mechanical behaviour of soft tissue is influenced by its elastic and viscous characteristics. Therefore, the aim of this study was to develop a validated method to characterise the viscoelastic properties of soft tissues based on ultrasound elastography data. Approach. Plantar soft tissue was chosen as the tissue of interest, and gelatine-phantoms replicating its mechanical properties were manufactured for validation of the protocol. Both plantar soft tissue and the phantom were scanned using Reverberant shear wave ultrasound (US) elastography at 400–600 Hz. Shear wave speed was estimated using the US particle velocity data. The viscoelastic parameters were extracted by fitting the Young’s modulus as a function of frequency derived from the constitutive equations of the eight rheological models (four classic and their fractional-derivative versions) to the shear wave dispersion data. Furthermore, stress-time functions derived from the eight rheological models were fitted to the phantom stress-relaxation data. Main results. The viscoelastic parameters estimated using elastography data based on the fractional-derivative (FD) models, compared to the classic models, were closer to those quantified using the mechanical test. In addition, the FD-Maxwell and FD-Kelvin–Voigt models showed to more effectively replicate the viscoelastic behaviour of the plantar soft tissue with minimum number of model parameters ( = 0.72 for both models) . Hence the FD-KV and FD-Maxwell models can more effectively quantify the viscoelastic characteristics of the soft tissue compared to other models. Significance. In this study, a method for mechanical characterisation of the viscoelastic properties of soft tissue in ultrasound elastography was developed and fully validated. An investigation into the most valid rheological model and its applications in plantar soft tissue assessment were also presented. This proposed approach for the characterisation of viscous and elastic mechanical properties of soft tissue has implications in assessing the soft tissue function where those can be used as markers for diagnosis or prognosis of tissue status.

A 16nm All-Digital Hardware Monitor for Evaluating Electromigration Effects in Signal Interconnects Through Bit-Error-Rate Tracking

The impact of Electromigration (EM) on the Bit-Error-Rate (BER) of signal interconnect paths was experimentally examined. An array-based test-vehicle for tracking Bit-Error-Rate (BER) degradation of signal interconnects subject to Direct-Current (DC) EM stress was implemented in a 16nm FinFET process. A unit interconnect path comprises five identical interconnect stages where each wire is driven by inverter based buffers. Accelerated EM stress testing is achieved entirely on-chip using metal heaters located directly above the devices-under-test (DUTs) and separate stress circuits driving both ends of the wire. The proposed test structure features a ring-based Voltage-Controlled-Oscillator (VCO), a bit-pattern generator and local BER sampling monitors which enable bitwise tracking of ‘0’ and ‘1’ errors separately, further simplifying the overall test-setup and allowing for high precision characterization of EM induced resistance shifts using only digital circuits. Measurement data collected from the 16nm prototype reveals unique insights into EM induced signal path degradation that was not available prior to this work. Our experimental studies suggest that monitoring the BER of an interconnect path could be used as a new metric for capturing EM induced resistance shifts in a real system, in lieu of the conventional approach which focuses on monitoring standalone wire resistances. Supplemental simulations showcasing the projected degradation in the interconnect path operating frequency as a function of stress time constructed from resistance traces sampled from identical wires implemented in the same process reaffirm the measurement trends.

Accelerated Stress Tests and Statistical Reliability Analysis of Metal-Oxide/GaN Nanostructured Sensor Devices

In this work, sensor die/process and packaging reliabilities of metal-oxide/GaN nanowire-based gas sensors have been studied for the first time, using industry standard accelerated lifetime tests, such as- High Temperature Operating Life, High Temperature Storage Life, Temperature Cycling Test and Highly Accelerated Stress Test. The metal-oxide functionalization used for sensing ethanol exposure in this study is ZnO. For all the tests, sample ZnO/GaN devices have been exposed to 500 ppm of ethanol in dry air at room temperature (20°C) to observe and record the degradation of signal to noise ratio (SNR) as a function of stress time and number of thermal cycles. Although no complete device failure was observed in any of the performed tests, gas sensing response kept decreasing gradually due to increasing stress. The lowering of the sensor response is believed to be due to gradual phase transformation of the receptor ZnO and baseline resistance increase. The method for estimating failure rate and lifetime of sensor devices has been discussed in detail. Using statistical data from the performed accelerated stress tests, chi-square distribution has been implemented to predict the failure rate and lifetime of GaN nanostructured sensor devices. The mean-time-to-failure (MTTF) of the stressed devices of this study is about 4 years.

Modeling Tool for Capacitive RF MEMS Operating Bias Voltage Optimization

In this paper, dielectric charging process in dielectrics under bias voltage is investigated. Dielectric materials, used in numerous devices in microelectronics, can be subjected to significant electrical stress. These high electric fields impact the device lifetime. Actuation voltage measurements of capacitive RF MEMS as a function of stress time have been performed. Results show that the actuation voltage varies because of charge storage in the dielectric thin film. In this work a simulation code has been developed to model charge transport phenomena in insulators. This model takes into account tunnel and thermal effects in the dielectric and at the dielectric-metal interfaces. Thanks to this model, charge carrier distribution in the dielectric layer can be calculated. The actuation bias shift versus time, which can be responsible for RF capacitive structure failure, can also be determined. Experimental results can be reproduced thanks to simulations. This simulation tool is then used to define the optimal operating voltage value for a given RF MEMS device. It may also be used to assist in device design in microelectronics. Indeed for a given material set, the optimal operating voltage value is calculated as a function of device properties.

Modeling of asymmetric degradation based on a non-uniform electric field and temperature in amorphous In–Ga–Zn–O thin film transistors

We propose a new local degradation model based on a non-uniform increase in donor-like traps (DLTs) determined by distributions of an electric field and measured device temperature in amorphous In–Ga–Zn–O (a-IGZO) thin film transistors (TFTs). A systematic investigation of the degradation model reveals that vertical field-dependent DLTs are essential for modeling of measured asymmetric electrical characteristics between the source and drain after positive gate and drain bias stressing. An increased temperature due to self-heating is found to play a role in intensifying the asymmetric degradation. From the individual simulation of measured transfer curves at different stress times, the model parameters and an asymmetry index as a function of stress time are extracted. It is expected that this novel methodology will provide new insight into asymmetric degradation and be utilized to predict the influence of electric field and heat on degradation under various bias-stress conditions in a-IGZO TFTs.

Effect of illumination and electric field intensity on the efficiency improvement of amorphous silicon tandem solar cells

The improvement of tandem hydrogenated amorphous/microcrystalline Si solar cells under prolonged exposure to reverse bias direct current electric fields and illumination has been investigated. In this work, the authors show that the application of reverse bias stress in the presence of illumination slows down the solar cell ageing kinetics (caused mainly by the Staebler–Wronski effect and by the increase in the series resistance) and, in suitable conditions, it produces an improvement of the solar cell characteristic parameters as a function of stress time. The authors discuss the effect of temperature, electric field intensity, and illumination level.

Prospectively of Carbon-Doped Indium-Tungsten-Oxide Channel TFT for Bias Stress Instability

Introduction InOx-based thin film transistors (TFTs) such as In-Ga-Zn-O, In-Ti-O, In-W-O, and In-Si-O have been widely investigated. We also reported carbon doped In-Si-O (In1-xSixOC) as channel material because of the highest bond dissociation energy of 1076 kJ/mol between carbon and oxygen. The turn on voltage shift (ΔV on) of In0.80Si0.20OC (C: 0.9 at. %) and In0.79Si0.21O TFT were 0 V and -0.2 V, respectively. The ΔV on of the In0.80Si0.20OC (C: 0.9 at. %) TFT was improved 0.2 V compared to that of In0.79Si0.21O TFT under positive gate bias stress (PBS) due to excess electron trapping reduction. Although In0.80Si0.20OC showed a good stability, the base In0.79Si0.21O TFT shows a low mobility of 7.7 cm2/Vs. To archive both high mobility and reliability, we investigated carbon doped In-W-O (In1-xWxOC) TFT because the In0.98W0.02O has a high mobility (> 39.0 cm2/Vs). In this paper, we studied transistor properties of In1-xWxOC TFT. We also discuss effect of carbon in In-W-O by comparing the stability between In1-xWxO and In1-xWxOC TFTs. Experiment The In1-xWxOC TFTs were fabricated on p++-Si (0.00099 Ω·cm) with 300-nm-thick thermal-oxide layers. 10-nm-thick In1-xWxOC films were formed on the substrates through a stencil shadow mask at room temperature by co-sputtering using In2O3 and WC targets under an Ar/O2 atmosphere at 0.2 Pa with PO 2 = 0.08 Pa. The XW of In1-xWxOC films were controlled in the range of 0.02 ~ 0.06 by changing the sputtering power for each target. Then, the post deposition annealing (PDA) was performed at 300 °C for 60 min in air. Finally, Au (100 nm)/Ti (10 nm) layer as source and drain electrodes were deposited by thermal evaporation method. The channel length and width of the TFT used in this study were 350 and 1000 μm, respectively. Results and Discussion The carbon content and chemical bond state of In1-xWxOCfilms were examined by X-ray photoelectron spectroscopy (XPS) measurements. The atomic ratio of carbon in In0.98W0.02OC, In0.96W0.04OC, and In0.94W0.06OC films were 0.3, 0.4, and 1.2 at. %, respectively. Moreover, the C1s peaks at 285 and 290 eV are observed after PDA, and attribute to W-C and O-C=O bonds in the In1-xWxOC films, respectively. Figure 1 (a) and (b) show comparison of the ΔV on of the In0.96W0.04OC and the In0.98W0.02O TFTs as a function of stress time under PBS and NBS conditions, respectively. The subthreshold swing (S.S.), on/off current ratio (I on/I off), threshold voltage (V th) and saturation field-effect-mobility (μ sat) values of In0.96W0.04OC TFT were 0.52 V/decade, 1.0×109, 0.4 V and 5.6 cm2/Vs, respectively at the initial state. The ΔV on in the In0.96W0.04OC TFT was 4.4 V after the PBS application of 10800 s (Fig. 1(a)). The ΔV on of the In0.96W0.04OC TFT was always smaller than that of In0. 98W0. 02O film under PBS. This indicates that trap state in In1-xWxOC channel were suppressed by introducing carbon. On the other hand, it is clear that the ΔV on (~ 0 V) of In0.96W0.04OC TFT was improved significantly compared to that (-0.5 V) of In0.98W0.02O TFT under the NBS of 5000 s. It was reported that the large ΔV on under NBS is due to the abnormal VO formation in oxide channel for GIZO TFT [7]. Therefore, this indicates that excess abnormal VO formation in In1-xWxOC channel is suppressed by introducing carbon. Conclusions We succeeded to introduce carbon (0.3-1.2 at. %) into In-W-O by co-sputtering WC and In2O3 targets. The S.S., I on/I off, V th and μ sat values of In0.96W0.04OC TFT were 0.52 V/decade, 1.0×109, 0.4 V and 5.6 cm2/Vs, respectively. The ΔV on of In0.96W0.04OC TFT was suppressed compared to that of In0. 98W0. 02O film under PBS. The ΔV on of In0.96W0.04OC TFT was not changed stress time up to 5000 s. The In0.96W0.04OC TFT is useful to reduce ΔV on under both the PBS and the NBS.

Study of stability of solution-processed dielectric film under electrical stress

In this work, a methodology to analyze the stability of solution-processed transparent dielectric based on Spin-on Glass under electrical stress is presented. Electrical stress is applied to MOS capacitors at different voltage values. The capacitance – voltage curves are analyzed as a function of stress time and voltage applied. After a rest period of 24 and 48 h, the capacitance – voltage curves were measured to compare performance. The results are applicable to Thin-film Transistors in order to study their stability and avoid confusion with the defect creation in channel layer mechanism.

Effect of Light Intensity and Wavelength on a-Ingazno Thin Film Transistors Under Negative Bias Illumination Stress

Amorphous InGaZnO (a-IGZO) has excellent properties such as high on/off ratio, good uniformity, and low processing temperature, so they are promising channel material for thin film transistors (TFTs). Instability mechanism of a-IGZO TFTs depending on environmental effects, bias, temperature and illumination stress was widely investigated and reported. Especially in the case of negative bias stress, degradation is accelerated under illumination and many studies have been done to clarify the causes. However, the effects of wavelength and intensity of light during negative bias stress under illumination stress (NBIS) have not been fully explained yet. Transfer characteristics of a-IGZO TFTs with back channel etch structure were measured after NBIS is applied. Gate voltage of -40 V was applied at 90 °C for 4000 s while drain and source were grounded. Illumination from white LED was passed through blue, green and red color filters which have peak wavelengths of 450 nm, 530 nm and 700 nm, respectively. To verify the relationship between intensity of light and degradation, measurements were done with various intensities of light. Severe negative shifts in transfer curve was shown under NBIS with blue light, while relatively little shifts were shown with green, red light and in darkness (Fig. 1). Apparent degradation in subthreshold slope was observed with blue light, which represents the creation of sub-gap states (Fig. 1d). Shifts in Vth as a function of stress time were extracted with various illumination conditions (Fig.2). The intensities of illumination were 4500 lux for white and 100 lux for blue, green and red light. Despite of much lower intensity compared to that of white light, blue light induced comparable amount of Vth shifts with that of white light; Vthshifts after 4000 s of stress were about -17.7 V for white and -16.3 V for blue light, but were only about -1.0 V for green light, -0.8 V for red light and -0.7 V for in darkness. To clarify the effect of intensity in blue light, we adjusted the intensity as 100, 50, 25, 12 and 6 lux with the same stress condition. Amount of Vth shifts were not significantly altered until the illumination was reduced to 25 lux, but started to show drastic decrease below 25 lux (Fig. 3a). It indicates that threshold intensity of illumination and saturation phenomenon exist in NBIS induced degradation of IGZO TFTs. Measurements were repeated at 60 °C and Vthshifts as a function of intensity was plotted with different temperature condition (Fig. 3b). Saturation phenomenon started at higher intensity of light (50 lux) for low temperature, which can be interpreted in terms of activation energy. In this work, we investigated the effect of wavelength and intensity of light in degradation of a-IGZO TFTs induced by NBIS. We discovered the existence of threshold light intensity and observed saturated behavior in Vth shifts under NBIS with respect to intensity. We will explain degradation mechanism in NBIS depending on wavelength and introduce new instability mechanism related to intensity of light. Figure 1

Role of electric field and electrode material on the improvement of the ageing effects in hydrogenated amorphous silicon solar cells

The effects of prolonged exposure to reverse bias DC electric fields and illumination as a function of temperature in hydrogenated amorphous Si (a-Si:H) photovoltaic p–i–n cells have been investigated. These are strongly affected by the well known Staebler–Wronski effect, occurring during light soaking of a-Si:H photovoltaic cells. In this work we show that the application of a reverse bias stress in presence of illumination not only slows down the solar cell ageing kinetics but even produces an improvement of the cells parameters as a function of stress time. We discuss the effect of temperature, electric field intensity and illumination level. We also show that different types of bottom contact over which the a-Si:H is grown by PECVD have a strong influence on the recovery-improvement kinetics: SnO:F (FTO) transparent conductive oxide (TCO) and molybdenum bottom contacts to the p-type a-Si:H layer are here compared. Finally, we demonstrate that an analogous improvement (reduction) of sheet resistance is observed in single thin films of doped a-Si:H deposited on SiO2 under the application of high intensity electric fields.

Negative bias temperature instability threshold voltage shift turnaround in SiGe channel MOSFETs

Negative bias temperature instability (NBTI) has been measured at various temperatures in high-k gate insulator MOSFETs with buried Si0.65Ge0.35 channels and with regular Si surface channels. Previous studies on both surface channel Si devices and Si1−xGex buried channel devices provide evidence for net positive charge trapping as a function of electrical stressing time albeit reduced for the case of Si1−xGex compared to the Si case. In our case, for buried Si0.65Ge0.35, the authors find initial negative charge trapping followed by positive charge trapping at longer times, typically >10−1 s. The effect is accentuated at higher temperatures and yields a turnaround in the measured threshold voltage shift as a function of stress time. Closer examination of NBTI in high-k gate, Si surface devices stressed at room temperature and 90 °C suggests both electron and hole trapping may be present there although the majority effect is hole trapping.

Cu Migration and its Impact on the Metastable Behavior of CdTe Solar Cells

ABSTRACTIn this work, we report on development of one-dimensional reaction-diffusion simulator needed to understand the kinetics of Cu-related metastabilities observed in CdTe PV devices. Evolution of intrinsic and Cu-related defects in CdTe solar cells has been studied in time-space domain self-consistently with free carrier transport. Resulting device performance was simulated as a function of stress time, thus showing pronounced effect that the evolution of associated acceptor and donor states can cause on device characteristics. Although 1D simulation has intrinsic limitations when applied to poly-crystalline films, the results presented confirm the validity and the potential of the approach presented in better understanding of the performance and metastabilities of CdTe photovoltaic devices.

Insulation Resistance Degradation in Ni–BaTiO3Multilayer Ceramic Capacitors

Insulation resistance (IR) degradation in Ni-BaTiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> multilayer ceramic capacitors has been characterized by the measurement of both time to failure (TTF) and direct current leakage as a function of stress time under highly accelerated life test conditions. The measured leakage currenttime dependence data fit well to an exponential form, and a characteristic growth time τSD can be determined. A greater value of τSD represents a slower IR degradation process. Oxygen vacancy migration and localization at the grain boundary region results in the reduction of the Schottky barrier height and has been found to be the main reason for IR degradation in Ni-BaTiO3 capacitors. The reduction of barrier height as a function of time follows an exponential relation of φ(t) = φ(0)e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2Kt</sup> , where the degradation rate constant K = K <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> e(-E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</sub> /kT) is inversely proportional to the mean TTF (MTTF) and can be determined using an Arrhenius plot. For oxygen vacancy electromigration, a lower barrier height φ(0) will favor a slow IR degradation process, but a lower φ(0) will also promote electronic carrier conduction across the barrier and decrease the IR. As a result, a moderate barrier height φ(0) (and therefore a moderate IR value) with a longer MTTF (smaller degradation rate constant K) will result in a minimized IR degradation process and the most improved reliability in Ni-BaTiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> multilayer ceramic capacitors.

Improvement in gate bias stress instability of amorphous indium-gallium-zinc oxide thin-film transistors using microwave irradiation

In this study, we evaluated the effects of microwave irradiation (MWI) post-deposition-annealing (PDA) treatment on the gate bias stress instability of amorphous indium-gallium-zinc oxide thin-film transistors (a-IGZO TFTs) and compared the results with a conventional thermal annealing PDA treatment. The MWI-PDA-treated a-IGZO TFTs exhibited enhanced electrical performance as well as improved long-term stability with increasing microwave power. The positive turn-on voltage shift (ΔVON) as a function of stress time with positive bias and varying temperature was precisely modeled on a stretched-exponential equation, suggesting that charge trapping is a dominant mechanism in the instability of MWI-PDA-treated a-IGZO TFTs. The characteristic trapping time and average effective barrier height for electron transport indicate that the MWI-PDA treatment effectively reduces the defects in a-IGZO TFTs, resulting in a superior resistance against gate bias stress.

A Correlation Between Oxygen Vacancies and Reliability Characteristics in a Single Zirconium Oxide Metal-Insulator-Metal Capacitor

A correlation between reliability characteristics and failure mechanisms for time-dependent dielectric breakdown for a single ZrO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> metal-insulator-metal capacitor has been studied. Frenkel-Poole emission was the dominant mechanism in the high electric field region. The extracted dynamic constant and trap energy level were 4.013 and 0.963 eV, respectively. The variation of α as a function of stress time under constant voltage stress (CVS) gradually decreased. Moreover, ΔC <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">stress</sub> /C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> under dynamic voltage stress was much greater than under CVS, which indicates that new defects and charge trapping could be generated in high-κ (HK) dielectric under dynamic voltage stress under negative voltage as well as positive voltage. The extracted average value of the Weibull slope (β) at 125°C was in the range 1.3-1.6. The average field acceleration parameter was ~8.67 cm/MV, and an effective dipole moment of bond breakage peff was ~29.73e Å. The thermochemical model (E model) suggested that the oxygen vacancies induced by the dipolar energy contribution (p · Eloc) easily caused bond breakage in the HK dielectric. The energy required to form another V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> was weakened to the bond strength of polar molecules. The characteristic breakdown strength (EBD) of ZrO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> was 6.31 MV/cm, and the extracted activation energy AH <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> * was 1.874 eV when considering E model.

Thermoreflectance microscopy analysis on self-heating effect of short-channel amorphous In-Ga-Zn-O thin film transistors

Self-heating effect is recently considered to play an essential role in the degradation of amorphous oxide thin film transistors (TFTs). Previous thermal analysis on amorphous oxide TFTs based on conventional infrared thermography, however, had limitations in studying short-channel TFTs due to its low spatial-resolution. Here, we investigated self-heating effect of short-channel amorphous In-Ga-Zn-O TFTs by using high-resolution thermoreflectance microscopy. For the TFT with a channel length of 15 μm and a distance of 10.8 μm between source and drain electrodes on an etch stopper, the device temperature due to self-heating reached 70–80 °C, and local heating arose close to the center of the channel compared to the drain side in the literature. The channel length dependence of thermal distribution revealed that the asymmetry of local heating weakened with the decreasing channel length due to a heat dissipation by the source and drain electrodes. Transient thermal analysis under a bias stress unveiled that the maximum temperature as a function of stress time strongly depends on bias stress conditions. The temporal behavior of temperature is possibly attributed to the interaction between self-heating and local degradation.

Correlations between BTI-Induced Degradations and Process Variations on ASICs and FPGAs

We analyze the correlation between BTI (Bias Temperature Instability) -induced degradations and process variations. Those reliability issues are correlated. BTI is one of the most significant agingdegradations on LSIs. Threshold voltages of MOSFETs increase with time when biases stress their gates. It shows a strong effect of BTI on highly scaled LSIs in the same way as the process variations. The accurate prediction of the combinational effects is indispensable. We should analyze both aging-degradations and process variations of MOSFETs to explain the correlation. We measure frequencies of ROs (Ring Oscillators) of 65-nm process test circuits on two types of LSIs, ASICs and FPGAs. There are 98 and 837 ROs on our ASICs and FPGAs respectively. The frequencies of ROs follow gaussian distributions. We describe the highest frequency group as the “fast” conditon, the average group as the “typical” conditon and the lowest group as the “slow” conditon. We measure the aging-degradations of the ROs of the three conditions on the accelerated test. The degradations can be approximated by logarithmic function of stress time. The degradation at the “fast” condition has a higher impact on the frequency than the “slow” one. The correlation coefficient is 0.338. In this case, we can define a smaller design margin for BTI-induced degradations than that without considering the correlation because the degradation at the “slow” conditon is smaller than the average and the fast. key words: BTI, process variation, reliability

A Theory in Finite Differences for Computation of Interchanging Principal Stresses and Principal Axes Rotation

Suppose consecutive ordinates of three arbitrary and nonproportional stress-time functions of plane state of stress are entered into a computer by a little finite time step. The theory proposed solves the following problem: correct computation of the ordinates of the principal stress-time functions and the angle of principal axes rotation. This problem is not as simple as researchers approached it prior to the computer era. First of all, the correct solution for the principal stresses and the principal axes rotation require correct interchange of the principal stresses while computing them, i.e., correct interchange of the plus/minus signs in the well-known equations for them. For the interchange analysis, an ellipse of stress transformation in the three-dimensional stress-coordinate space is revealed. By changing a coordinate scale, the ellipse turns into a circumference that is an analog to, but different from, a Mohr circle. The correct solution also requires treating the principal axes rotation in little finite differences per little time differences during which little finite elements appear as building the stressing path in the three-dimensional stress-coordinate space. Based on the ellipse/circumference mentioned, three interchange conditions are revealed. The third one is the most important. And, a necessity is also revealed for dividing some stressing path's elements into two subelements. Based on all the findings, the main commands of an algorithm for computing the ordinates of the principal stress-time functions and the angle of principal axes rotation are presented. The correct solution of the problem has been achieved thanks to new notions taken from the so-called integration of damage differentials (IDD) theory. In fact, the paper presents a new contribution to the variable plane stress state analysis.

Trapping Time Characteristics of Carriers in a-InGaZnO Thin-Film Transistors Fabricated at Low Temperatures for Next-Generation Displays

The effect of low-temperature annealing treatment for various durations on the stability of amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors was investigated. By this treatment, IGZO TFTs showed enhanced electrical characteristics and better stability under positive gate bias stress with increasing annealing time up to 18,000 s. For all VG stresses at different annealing times, the experimentally measured threshold voltage shift (ΔVth) as a function of stress time was precisely modeled with a stretched-exponential function. ΔVth was generated by carrier trapping, not by defect creation. It was verified that the decrease of interface trap state density (Nit) and free carriers resulted in the decrease of ΔVth with increasing annealing time. However, the characteristic trapping time of the carriers increased up to 5.3 × 103 s with increasing annealing time to 7,200 s and then decreased, implying that the interface quality between active layer/insulator was deteriorated with further annealing. In this study, successful fabrication of IGZO TFTs by post treatment with optimized duration is demonstrated for flexible display applications.