Abstract

Negative bias temperature instability (NBTI) has been measured at various temperatures in high-k gate insulator MOSFETs with buried Si0.65Ge0.35 channels and with regular Si surface channels. Previous studies on both surface channel Si devices and Si1−xGex buried channel devices provide evidence for net positive charge trapping as a function of electrical stressing time albeit reduced for the case of Si1−xGex compared to the Si case. In our case, for buried Si0.65Ge0.35, the authors find initial negative charge trapping followed by positive charge trapping at longer times, typically >10−1 s. The effect is accentuated at higher temperatures and yields a turnaround in the measured threshold voltage shift as a function of stress time. Closer examination of NBTI in high-k gate, Si surface devices stressed at room temperature and 90 °C suggests both electron and hole trapping may be present there although the majority effect is hole trapping.

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