Fully Integrated Voltage Regulators Research Articles

Improved On-Chip Inductor Design for Fully Integrated Voltage Regulators

This article presents a simple procedure to optimally design an on-chip spiral inductor, which is normally a major challenge in fully integrated voltage regulator (FIVR) applications. To develop the design method, a simplified model is proposed and evaluated that describes the inductance and resistance values of an on-chip spiral inductor according to its geometric properties. Maximizing the quality factor -based on the inductor total resistance- and minimizing the power loss -based on the inductor total resistance and its current waveform- in the minimum possible chip area are two different goals that are achieved. Two design methods are presented to provide optimal geometric specifications of the on-chip inductor. The design methods are simple and do not require complex simulation iterations. In addition, 3-D electromagnetic simulation is used to extract the characteristics of the designed on-chip spiral inductors to perform comparisons and the verification of the effectiveness of the proposed design methods.

A Machine Learning-Based Method for Tuning the Control Loop of Fully Integrated Voltage Regulators

Fully integrated voltage regulators (FIVRs) have been introduced in the latest generation of microprocessors to improve the power efficiency and performance of processors. FIVR has a feedback control loop that regulates the output voltage in the presence of load current transients, input voltage noise, and variations or drifts in component parameters. The feedback control loop consists of a type-III op-amp compensator (CPS) with programmable resistance and capacitance ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> ) values. The <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> values are tuned in pre-Si and post-Si stages to achieve the desired stability and transient response. The practical op-amp CPS is nonideal, and it is difficult to model its behavior using analytical models. Hence, tuning methods based on analytical models such as the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$k$ </tex-math></inline-formula> -factor method cannot be used to tune the op-amp CPS. Manual tuning of the op-amp <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> values or tuning using traditional optimization methods needs either many simulations in the pre-Si stage or many measurements in the post-Si stage. The output impedance and the droop response of FIVR need to be also considered while tuning the control loop. Thus, the tuning of FIVR control loop remains a challenge with significant time and effort being spent on identifying the optimal <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> values. A machine learning method based on Bayesian optimization (BO) is proposed to tune the FIVR control loop and is demonstrated to reduce the number of simulations in the pre-Si stage significantly.

A State-Space-Based Method to Model Vccin Feedthrough Noise in Microprocessors With Fully Integrated Voltage Regulators

Modern high-performance server microprocessors need to integrate multiple intellectual property (IP) blocks in a single chip to achieve higher performance. Due to the diverse supply voltage requirements of these IP blocks, their supply voltages are generated locally on the chip using fully integrated voltage regulators (FIVRs). FIVR is designed using on-chip power bridges, bridge drivers, control circuits, on-chip metal–insulator–metal (MIM) capacitors, package inductors, and package power planes. The input power supply (Vccin) of all the FIVRs is shared to minimize the platform cost and is generated using a voltage regulator module (VRM) on the motherboard. The noise coupling between FIVRs due to the common input supply is referred to as the Vccin feedthrough noise. The existing method of modeling the Vccin feedthrough noise is based on circuit simulation. Circuit models are highly complex as different components such as the FIVR power bridges, bridge drivers, MIM capacitors, package inductors, package power planes, and the Vccin network need to be modeled. Convergence issues are very frequent in full chip circuit simulations and it typically takes many iterations. Hence design optimization is difficult to carry out using circuit simulations. In this article, a state-space-based time-domain method is proposed to model the Vccin feedthrough noise based on G-parameters and S-parameters of the FIVR and the Vccin network. The state-space models are generated using the vector-fitting algorithm. The proposed method simplifies the construction of the Vccin feedthrough models and improves the convergence time.

Fully Integrated Switched-Inductor-Capacitor Voltage Regulator With 0.82-A/mm2 Peak Current Density and 78% Peak Power Efficiency

Fully integrated voltage regulators (FIVRs) can improve the performance and reduce the power consumption of a system-on-chip (SoC) by providing point-of-load voltage regulation with dynamic voltage scaling. The desirable attributes of FIVRs include high power efficiency, high power density, and fast transient response, which are difficult to achieve due to on-chip area constraint and parasitic effects. Low-quality and low-density on-chip inductors and capacitors are currently the main performance-limiting factors. This article presents a switched-inductor-capacitor (SIC) voltage converter that can operate more efficiently with compact on-chip air-cored metal-tracked inductors than existing step-down voltage converters. The SIC converter consists of an inductor, a flying capacitor, and three power switches, and it can provide fine-grained voltage regulation by using pulsewidth-modulation (PWM) control. The unique SIC converter topology eases the on-chip inductor integration by positioning the inductor at the input power supply and reducing the current stress of the inductor. A proof-of-concept fully integrated SIC voltage regulator is fabricated in a 65-nm CMOS process, with an area of 1.3 mm × 0.5 mm excluding pads. The output voltage can be regulated from 0.6 to 0.9 V given a 1.2-V input power supply. The output voltage ripple is below 56 mV over the entire range of output voltages and load currents. The peak power efficiency is 78% at an output of 0.9 V and 406 mA. The peak power density is 730 mW/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and the peak current density is 820 mA/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Design of Soft-Switching Hybrid DC-DC Converter with 2-Phase Switched Capacitor and 0.8nH Inductor for Standard CMOS Process

A soft-switching hybrid DC-DC converter with a 2-phase switched capacitor is proposed for the implementation of a fully-integrated voltage regulator in a 65 nm standard CMOS process. The soft-switching operation is implemented to minimize power loss due to the parasitic capacitance of the flying capacitor. The 2-phase switched capacitor topology keeps the same resonance value for every soft-switching operation, resulting in minimizing the voltage imbalance of the flying capacitor. The proposed adaptive timing generator digitally calibrates the turn-on delay of switches to achieve a complete soft-switching operation. The simulation results show that the proposed soft-switching hybrid DC-DC converter with a 2-phase 2:1 switched capacitor improves the efficiency by 5.1% and achieves 79.5% peak efficiency at a maximum load current of 250 mA.

A Light-Load Efficient Fully Integrated Voltage Regulator in 14-nm CMOS With 2.5-nH Package-Embedded Air-Core Inductors

Fully integrated voltage regulators (FIVRs) offer many advantages, such as fine-grained power management, fast transient response, and reduced form factor. This article addresses light-load efficiency in FIVRs with nH-scale air-core inductors. The challenges of implementing efficient discontinuous conduction mode (DCM) operation at high switching frequencies are discussed, which include zero current detection, inductor ac-loss effects, and power delivery network (PDN) resonances. A prototype in 14-nm CMOS is presented, which shows the DCM operation at up to 70 MHz with a peak efficiency of 88% for 1.6–1.2-V conversion.

System-Level Power Analysis of a Multicore Multipower Domain Processor With ON-Chip Voltage Regulators

In this paper, we study two different ON-chip power delivery schemes, namely, fully integrated voltage regulator (FIVR) and low-dropout regulator (LDO), and analyze their effect on total system power under process variation, assuming a realistic dynamic voltage–frequency scaling (DVFS) system. The impact of different task scheduling algorithms on the overall system power was also analyzed. We find that in a hypothetical 256-core processor, under a per-core DVFS assumption, the FIVR-based power delivery consumes 20% less power than the LDO-based one for a 50% throughput. However, as the number of cores in the processor reduces, the difference in power consumption between the FIVR-based and LDO-based power delivery schemes becomes smaller. For example, in the case of a 16-core processor with per-core DVFS capability, FIVR-based design was found to consume about the same power as the LDO-based design.

The Xeon® Processor E5-2600 v3: a 22 nm 18-Core Product Family

The next generation enterprise Xeon server processor maximum configuration supports 18 dual-threaded 64 bit Haswell cores, 45 MB L3 cache, 4 DDR4-2133 MHz memory channels, 40 8 GT/s PCIe lanes, and 40 9.6 GT/s QPI lanes. The processor has 5.56 B transistors on a 31.9 mm × 20.8 mm die in Intel's Hi-K metal-gate tri-gate 22 nm CMOS technology with 11 metal layers and achieves up to 33% performance boost. The design supports a wide range of configurations including thermal design power ranging from 55 to 160 W and frequencies ranging from 1.6 to 3.7 GHz. Key architectural innovations include the addition of AVX2 technology, DDR4, and fully integrated voltage regulators (FIVR) that enable per core p-states and uncore frequency scaling.

Package Inductors for Intel Fully Integrated Voltage Regulators

Intel fourth-generation and fifth-generation Core microprocessors are powered by high-frequency integrated switching voltage regulators. The inductors required to implement these regulators are constructed using the routing layers of conventional organic flip chip packaging. This paper provides an overview of the construction of these inductors including representative results from production packages. Measured inductors reported in this paper span from 1 to 6.7 nH under 2.4 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and achieve Q of up to 24 at 140 MHz (the switching frequency).

Haswell: A Family of IA 22 nm Processors

We describe the 4th Generation Intel® Core™ processor family (codenamed “Haswell”) implemented on Intel® 22 nm technology and intended to support form factors from desktops to fan-less Ultrabooks™. Performance enhancements include a 102 GB/sec L4 eDRAM cache, hardware support for transactional synchronization, and new FMA instructions that double FP operations per clock. Power improvements include Fully-Integrated Voltage Regulators ( ~ 50% battery life extension), new low-power states (95% standby power savings), optimized MCP I/O system (1.0-1.22 pJ/b), and improved DDR I/O circuits (40% active and 100x idle power savings). Other improvements include full-platform optimization via integrated display I/O interfaces.