A Machine Learning-Based Method for Tuning the Control Loop of Fully Integrated Voltage Regulators

Abstract

Fully integrated voltage regulators (FIVRs) have been introduced in the latest generation of microprocessors to improve the power efficiency and performance of processors. FIVR has a feedback control loop that regulates the output voltage in the presence of load current transients, input voltage noise, and variations or drifts in component parameters. The feedback control loop consists of a type-III op-amp compensator (CPS) with programmable resistance and capacitance ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> ) values. The <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> values are tuned in pre-Si and post-Si stages to achieve the desired stability and transient response. The practical op-amp CPS is nonideal, and it is difficult to model its behavior using analytical models. Hence, tuning methods based on analytical models such as the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$k$ </tex-math></inline-formula> -factor method cannot be used to tune the op-amp CPS. Manual tuning of the op-amp <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> values or tuning using traditional optimization methods needs either many simulations in the pre-Si stage or many measurements in the post-Si stage. The output impedance and the droop response of FIVR need to be also considered while tuning the control loop. Thus, the tuning of FIVR control loop remains a challenge with significant time and effort being spent on identifying the optimal <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> values. A machine learning method based on Bayesian optimization (BO) is proposed to tune the FIVR control loop and is demonstrated to reduce the number of simulations in the pre-Si stage significantly.