Fully Depleted Silicon On Insulator Transistors Research Articles

Simulation of Total Ionizing Dose Effects Technique for CMOS Inverter Circuit.

The total ionizing dose (TID) effect significantly impacts the electrical parameters of fully depleted silicon on insulator (FDSOI) devices and even invalidates the on-off function of devices. At present, most of the irradiation research on the circuit level is focused on the single event effect, and there is very little research on the total ionizing dose effect. Therefore, this study mainly analyzes the influence of TID effects on a CMOS inverter circuit based on 22 nm FDSOI transistors. First, we constructed and calibrated an N-type FDSOI metal-oxide semiconductor (NMOS) structure and P-type FDSOI metal-oxide semiconductor (PMOS) structure. The transfer characteristics and trapped charge distribution of these devices were studied under different irradiation doses. Next, we studied the TID effect on an inverter circuit composed of these two MOS transistors. The simulation results show that when the radiation dose was 400 krad (Si), the logic threshold drift of the inverter was approximately 0.052 V. These results help further investigate the impact on integrated circuits in an irradiation environment.

Fully Depleted SOI Technology for Millimeter-Wave Integrated Circuits

Performances of high-frequency integrated circuits are directly linked to the analog and high frequency characteristics of the transistors, the quality of the back-end of line process as well as the electromagnetic properties of the substrate. Today, Partially Depleted Silicon-on-Insulator (SOI) MOSFET is the mainstream technology for RF SOI systems. Fully Depleted (FD) SOI MOSFET is foreseen as one of the most promising candidates for the development of future lower power wireless communication systems operating in the millimeter-wave range. The high frequency performances of FD SOI transistors are presented at room but also at cryogenic and high temperature. Recently published results for FD SOI switches and low noise amplifiers are summarized. And finally, the potential interest and challenges to move from standard to high resistivity FD SOI substrates are discussed.

Efficient electrical characteristics estimation techniques for sub-20-nm FDSOI integrated circuits with nonrectangular gate patterning effects

In subwavelength lithography, printed patterns on the silicon wafer suffer from geometric distortions and differ from the original design. These nonrectangular patterns can seriously affect electrical characteristics and circuit performances. We extend the verification of location-dependent weighting method and further propose three single equivalent gate length (EGL) extraction methods for representing each nonrectangular gate (NRG) transistor with a single EGL model. These methods are applied to sub-20-nm fully depleted silicon on insulator (FDSOI) circuits to predict the postlithography performances. An in-house extreme ultraviolet lithography simulation tool is utilized for nonrectangular pattern simulation. Shape information is imported to TCAD to construct three-dimensional nonrectangular FDSOI transistor models. The accuracy of the location-dependent weighting method and EGL extraction methods is verified with TCAD circuit simulations. Preliminary simulation results indicate that weighting factors can improve the accuracy of electrical characteristics estimation, especially in leakage current analysis. On average, the EGLs extracted from off-state only data, and from data lumping both off- and on-states, respectively, can each predict SRAM electrical characteristics with overall error <1 % , or a factor of 5 accuracy improvement over the EGLs extracted without the weightings. These methods could be used to simulate large-scale sub-20-nm FDSOI circuits with NRG transistors caused by nonideal optical effects.

Analysis of single-event effects in selected BOX-based FDSOI transistor and inverter

The existence of buried oxide aggravates the self-heating effect (SHE) in fully depleted silicon-on-insulator (FDSOI) device. To reduce SHE, a new structure named selected BOX-based (SELBOX) FDSOI transistor is introduced in this work, and the single-event effect (SEE) is evaluated by two-dimension TCAD simulation. The location and size of open window are found to have evident influence on SEE in SELBOX devices. Suffering from the transient current in transistor level, single-event transient (SET) might appear in the inverter based on SELBOX technology when the heavy ions strike at the low level of input signal. The underlying physical mechanism is explored and discussed. This work provides a radiation hardened foundation for FDSOI technology in the future extreme environment electronics applications.

Empirical Large-Signal Modeling of mm-Wave FDSOI CMOS Based on Angelov Model

This article presents a systematic empirical modeling approach in fully depleted silicon-on-insulator (FDSOI) CMOS for large-signal simulation in power amplifier applications. The model is constructed from multibias S-parameter measurements up to 67 GHz. The frequency dispersions in transconductance and output conductance are addressed by two independent radio frequency (RF) current sources. Angelov's current formula is modified to adapt to the FDSOI transistors. Load-pull measurements are performed for the large-signal verification in a non-50-Ω environment. The model accurately predicts the nonlinear characteristics of the device under test and the harmonic components. The time-domain waveforms also show excellent agreement to the simulation.

Simulation of Total Ionizing Dose (TID) Effects Mitigation Technique for 22 nm Fully-Depleted Silicon-on-Insulator (FDSOI) Transistor

Based on 22 nm ultrathin-body fully depleted silicon-on-insulator (UTB-FDSOI) transistors, we propose a novel structure of buried insulator layer aiming at total ionizing dose (TID) effects mitigation. Using technology computer-aided design (TCAD) tools, we focus on the influences of UTB-FDSOI devices with different structures and parameters on TID effects, such as buried oxide (BOX) layer thickness, buried Si3N4 layer, and electron traps. First, we construct four types of UTB-FDSOI N-type metal-oxide semiconductor (NMOS) devices numerically, in which the novel device features a buried silicon-oxide-nitride-oxide-silicon (SONOS) structure. Then, the transfer characteristics and trapped charge distribution of these devices are studied under different irradiation doses. It is known that a thinner BOX layer could lead to slighter TID effects, and the buried nitride layer and the electron traps could reduce the TID-induced leakage current ( $\text{I}_{\mathrm {off}}$ ). Employing these optimization structures for TID effects hardness, the innovative transistor shows much better resistance against TID effects compared to the conventional FDSOI transistors. In addition, the threshold voltage of the novel device could be increased by applying appropriate bias conditions, similar to those of programming SONOS memory, so that the $\text{I}_{\mathrm {off}}$ caused by TID irradiation further decreases. These results provide useful guidance for designers to achieve TID effects mitigation of SOI devices.

Self-Heating Effect in FDSOI Transistors Down to Cryogenic Operation at 4.2 K

Self-heating in fully depleted silicon-on-insulator (FDSOI) metal–oxide–semiconductor field-effect transistors (MOSFETs) is experimentally studied using the gate resistance thermometry technique, in a wide temperature range from 300 down to 4.2 K. We demonstrate that below 160 K, the channel temperature increase ( $\Delta {T}$ ) due to self-heating starts to deviate significantly from the linear variation with the dissipated power, leading to an apparent power dependent thermal resistance. This power dependence is interpreted in terms of temperature dependent thermal conductivity. The thermal resistance dependence on the active device temperature ( ${T}_{\text {Device}}$ ) indicates that the former one is mainly driven by the thermal conductivity of the oxide layer. Moreover, based on this dependence we reconstructed the channel temperature increase for each dissipated power and ambient temperature, and we found that the calculated values were in a good agreement with the experimental ones. Results indicate that even at low temperatures, thermal resistance does not depend significantly on the silicon channel thickness (ranging from 7 up to 24 nm), whereas the buried-oxide thinning (145 and 25 nm) strongly reduces the magnitude of the thermal resistance. Finally, this paper intends to fill the gap of experimental data concerning self-heating in advanced FDSOI transistors at low temperatures, revealing limitations and perspectives that should be taken into account for future work.

1T Pixel Sensor Based on FDSOI Transistor Optical Back Biasing

This paper presents the study of a monolithically integrated FDSOI-based pixel sensor, called FDPix. The FDPix consists in cointegrating a photodiode in the substrate of an fully depleted silicon on insulator (FDSOI) transistor. Its principle of operation is based on optical back biasing of FDSOI transistor characteristics under photodiode illumination. A reset mechanism is demonstrated using the back gate of the transistor and can be applied commonly to all pixels, allowing a very small footprint. The investigation is carried out by means of TCAD simulation, analytical modeling, and optoelectrical characterization to evaluate the sensor’s characteristics and to optimize the device technological parameters. The pixel exhibits two responses, linear response at low intensities and logarithmic response at high intensities, achieving a high dynamic range (DR) of 120–130 dB.

Non-Boolean Associative Processing Using FDSOI MOSFET-Based Inverter

Fully depleted silicon-on-insulator (FDSOI) MOSFET-based inverter is used as a distance computing cell (DCC) for non-Boolean associative processing system. Using back-gate bias in FDSOI transistors, the DCC shows excellent controllability of current characteristics of DCC. The system consumes 150 to 300 times lower energy than bulk CMOS-based Boolean implementation and requires lesser number of transistors. It also consumes lower area and energy than most of the other non-Boolean systems. Additionally, output voltage swing, recognition accuracy, and consumed energy in the system, can be controlled by applying proper back gate voltage, on the transistors of winner take all block and DCC.

Analysis of single-event transient sensitivity in fully depleted silicon-on-insulator MOSFETs

Based on 3D-TCAD simulations, single-event transient (SET) effects and charge collection mechanisms in fully depleted silicon-on-insulator (FDSOI) transistors are investigated. This work presents a comparison between 28-nm technology and 0.2-μm technology to analyze the impact of strike location on SET sensitivity in FDSOI devices. Simulation results show that the most SET-sensitive region in FDSOI transistors is the drain region near the gate. An in-depth analysis shows that the bipolar amplification effect in FDSOI devices is dependent on the strike locations. In addition, when the drain contact is moved toward the drain direction, the most sensitive region drifts toward the drain and collects more charge. This provides theoretical guidance for SET hardening.

Characterization of RF Noise in UTBB FD-SOI MOSFET

In this paper, we report the noise measurements in the RF frequency range for ultrathin body and thin buried oxide fully depleted silicon on insulator (FD-SOI) transistors. We analyze the impact of back and front gate biases on the various noise parameters; along with discussions on the secondary effects in FD-SOI transistors which contribute to the thermal noise. Using calibrated TCAD simulations, we show that the noise figure changes with the substrate doping and buried oxide thickness.

Thermal resistance modeling in FDSOI transistors with industry standard model BSIM-IMG

The channel in Fully Depleted Silicon On Insulator (FDSOI) transistors is completely isolated from the substrate via buried oxide (BOX) and from the sides by shallow trench isolations, which results in high thermal resistance (Rth). Further, Rth increases with reduction in channel length (Lg). In this paper, we have proposed a compact model for the geometry and temperature dependence of Rth in FDSOI transistors. The model is validated against experimental and Technology Computer Aided Design (TCAD) data. The proposed model is implemented in the independent multi-gate model (BSIM-IMG) for FDSOI transistors.

2.45 GHz 0.8 mW voltage-controlled ring oscillator (VCRO) in 28 nm fully depleted silicon-on-insulator (FDSOI) technology

MOS bulk transistor is reaching its limits: sub-threshold slope (SS), drain induced barrier lowering (DIBL), threshold voltage (VT) and VDD scaling slowing down, more power dissipation, less speed gain, less accuracy, variability and reliability issues. Fully depleted devices are mandatory to continue the technology roadmap. FDSOI technology relies on a thin layer of silicon that is over a buried oxide (BOx). Called ultra thin body and buried oxide (UTBB) transistor, FDSOI transistors correspond to a simple evolution from conventional MOS bulk transistor. The capability to bias the back-gate allows us to implement calibration techniques without adding transistors in critical blocks. We have illustrated this technique on a very low power voltage-controlled oscillator (VCO) based on a ring oscillator (RO) designed in 28 nm FDSOI technology. Despite the fact that such VCO topology exhibits a larger phase noise, this design will address aggressively the size and power consumption reduction. Indeed we are using the efficient back-gate biasing offered by the FDSOI MOS transistor to compensate the mismatches between the different inverters of the ring oscillator to decrease jitter and phase noise. We will present the reasons which led us to use the FDSOI technology to reach the specifications of this PLL. The VCRO exhibits a 0.8 mW power consumption, with a phase noise about −94 dBc/Hz@1 MHz.

Modeling the impact of substrate depletion in FDSOI MOSFETs

In this work, we have modeled the impact of substrate depletion in fully-depleted silicon-on-insulator (FDSOI) transistor and have extensively verified the model for both NMOS and PMOS with geometrical and temperature scaling. The model has an accurate behavior for C–V and I–V characteristics and preserves the smooth behavior of the high order derivatives. Model validation is done at 50nm technology node with state of the art FDSOI transistors provided by Low-power Electronics Association and Project (LEAP) and excellent agreement with the experimental data is achieved after parameter extraction.

Sub-30-nm hybrid lithography (electron beam∕deep ultraviolet) and etch process for fully depleted metal oxide semiconductor transistors

Fully depleted silicon on insulator (FDSOI) devices with high-k dielectrics and metal gate are promising candidates for sub-45-nm complementary metal oxide semiconductor technologies. At present, the gate length reduction becomes more and more difficult due to resist thickness diminution induced by critical dimension downscaling. In order to suppress resist thickness limitations, we have added a carbon layer with a SiO2 capping onto the conventional dielectric hard mask (SiO2 or Si3N4). In this study, FDSOI transistors with hafnium dielectric (HfO2), titanium nitride (TiN) metal gate were patterned by combining high resolution hybrid lithography (electron beam∕deep ultraviolet) and amorphous carbon hard mask. Full three-dimensional (3D) characterizations were carried out by using 3D atomic force microscope (CD-AFM from Veeco) to determine the best process window. Finally, after carbon hard mask trimming, sub-30-nm gate length transistors were achieved and successfully electrically tested.

Differential magnetoresistance technique for mobility extraction in ultra-short channel FDSOI transistors

Ultra-thin Silicon-on-Insulator (SOI) transistor has proved to offer advantages over bulk MOSFETs for high-speed, low power applications. However, there is still a strong need to obtain an accurate understanding of carrier transport and mobility behaviour in these advanced devices. In this work, magnetoresistance technique is used to perform mobility measurements in Fully-Depleted Silicon-on-Insulator (FDSOI) MOSFETs. This technique has the advantage of allowing channel mobility measurement from weak to strong inversion without requiring the knowledge of the transistor’s effective channel length. The influence of different scattering mechanisms in the channel is investigated in details by obtaining mobility values at low temperatures. A new differential method enabling mobility extraction from pure channel magnetoresistance corrected for source–drain series resistance is presented. After the correction, in devices with large series resistance an increase in the extracted mobility is obtained in strong inversion, where the channel resistance is small and conventional mobility extraction is most affected by the impact of series resistance.

Source-Bias Dependent Charge Accumulation in P+-Poly Gate SOI Dynamic Random Access Memory Cell Transistors

In this paper, we report the dynamic data retention problems caused by the transient leakage current in a cell transistor during the bit-line pull down operation in p+-poly gate fully depleted silicon-on-insulator (FD-SOI) dynamic random access memories (DRAMs) due to the source-induced charge accumulation (SICA) effect in the silicon thin film. Due to the inherent floating body effect in the FD-SOI transistor, charge accumulation in the silicon thin film becomes inevitable when the gate-to-source voltage (VGS) is smaller than the flat-band voltage (VFB). In order to eliminate the transient leakage current problem in p+-poly gate FD-SOI cell transistor, the ground-precharged bit-line (GPB) sensing method is introduced.