Efficient electrical characteristics estimation techniques for sub-20-nm FDSOI integrated circuits with nonrectangular gate patterning effects

Abstract

In subwavelength lithography, printed patterns on the silicon wafer suffer from geometric distortions and differ from the original design. These nonrectangular patterns can seriously affect electrical characteristics and circuit performances. We extend the verification of location-dependent weighting method and further propose three single equivalent gate length (EGL) extraction methods for representing each nonrectangular gate (NRG) transistor with a single EGL model. These methods are applied to sub-20-nm fully depleted silicon on insulator (FDSOI) circuits to predict the postlithography performances. An in-house extreme ultraviolet lithography simulation tool is utilized for nonrectangular pattern simulation. Shape information is imported to TCAD to construct three-dimensional nonrectangular FDSOI transistor models. The accuracy of the location-dependent weighting method and EGL extraction methods is verified with TCAD circuit simulations. Preliminary simulation results indicate that weighting factors can improve the accuracy of electrical characteristics estimation, especially in leakage current analysis. On average, the EGLs extracted from off-state only data, and from data lumping both off- and on-states, respectively, can each predict SRAM electrical characteristics with overall error <1 % , or a factor of 5 accuracy improvement over the EGLs extracted without the weightings. These methods could be used to simulate large-scale sub-20-nm FDSOI circuits with NRG transistors caused by nonideal optical effects.