Full-scale Input Research Articles

A 22.3-Bit Third-Order Delta-Sigma Modulator for EEG Signal Acquisition Systems

This paper presents a high resolution delta-sigma modulator for continuous acquisition of electroencephalography (EEG) signals. The third-order single-loop architecture with a 1-bit quantizer is adopted to achieve 22.3-bit resolution. The effects of thermal noise on the performance of the delta-sigma modulator are analyzed to reasonably allocate the switched-capacitor sizes for optimal signal to noise ratio (SNR) and minimum chip area. The coefficients in feedback path and input path are optimized to avoid the signal distortion under the full-scale input voltage range with almost no increase in total capacitance sizes. Fabricated in 0.5 µm CMOS technology and powered by a 5 V voltage supply, the proposed delta-sigma modulator can achieve 136 dB peak SNR with 16 Hz input and 137 dB dynamic range in 100 Hz signal bandwidth with an oversampling ratio of 512. The modulator dissipates 700 µA. The core chip area is 1.96 mm2. The modulator occupies 1.41 mm2 and the decimator occupies 0.55 mm2.

Design and Testing of a Prototype ASIC for the MTPC Readout at CSNS Back-n White Neutron Source

In this paper, a prototype Application Specific Integrated Circuit (ASIC) for the Multi-purpose Time Projection Chambers (MTPC) at Back-n White Neutron Source is presented. The ASIC integrates 16 readout channels and is fabricated in a 0.18 μm CMOS process. Each channel consists of a Charge Sensitive Amplifier (CSA), a Pole-Zero Cancellation (PZC), two bridged-T shapers, a baseline holder, and a fully differential output buffer. It provides selectable charge ranges of 2 pC and 10 pC, programmable peaking times from 110 ns to 1 μs, and an adjustable output common-mode voltage from 0.7 V to 1.25 V. The ASIC has already been tested and all the results meet the requirements. In the case of 100 pF input capacitance, 2 pC charge range, and 1 μs peaking time, it features a maximum Integral Non-Linearity (INL) of 0.48% and an Equivalent Noise Charge (ENC) of 0.749 fC, which makes the Signal-to-Noise Ratio (SNR) at full-scale input over 2600. In particular, a crosstalk rejection ratio of 63 dB is obtained in this prototype ASIC by using the baseline holder circuit in each channel to generate references for single-ended to differential conversion, isolating noise and crosstalk from the reference path.

An Energy-Efficient SAR ADC With a Coarse-Fine Bypass Window Technique

This paper presents a coarse-fine bypass window technique to improve the energy efficiency of the successive approximation register (SAR) analog-to-digital converter (ADC) by skipping unnecessary conversion cycles when the input signal is within the bypass windows. It utilizes the time information of the MSB comparison to coarsely detect the input range without a dedicated timing budget. Based on the coarse detection results, the fine bypass window is configured by reusing the digital-to-analog converter (DAC) to accurately detect the input signal. Due to the presence of the coarse detection, the multi-window detection and its corresponding bypass operation are realized to maximize the effectiveness of the bypass window technique. In addition, the MSB-spilt switching scheme is proposed to reduce the DAC switch-back energy. A prototype 8-bit SAR ADC equipped with the proposed technique is fabricated in a 65-nm CMOS process. At a 350-MS/s sampling rate with a Nyquist input, the measured signal-to-noise-plus-distortion ratio (SNDR) and spurious-free dynamic ranges (SFDR) are 44.9 dB and 63.9 dB, respectively. At a supply voltage of 1.2 V, the ADC consumes power of 1.58 mW with the full-scale sinusoidal input signal. The ADC achieves an effective number of bits (ENOB) of 7.17 bit, resulting in a figure-of-merit (FoM) of 31.3 fJ/conversion-step. The ADC core occupies an active area of 0.0096 mm2.

Development of a novel two-dimensional(2D) three-way(3W) fuel flow control servo valve with constant pressure difference

To solve the problems of large volume, and low integration of traditional electro-hydraulic servo valve with constant pressure differential fuel metering device, a new two-dimensional three-way constant pressure differential fuel flow control servo valve (2D3WFFCSV) is developed. It innovatively adopts the advantages of lightweight of “two-dimensional hydraulic technology”, The constant differential pressure function and flow regulation function are integrated into a two-dimensional (2D) main spool with two degrees of freedom (rotational and axial degrees of freedom). The flow control process of 2D3WFFCSV is as follows: firstly, the armature of the torque motor and the two-dimensional piston are coaxially installed at the end of the two-dimensional piston, so the torque motor can directly drive the two-dimensional piston to rotate; secondly the “hydraulic servo screw mechanism”, which can amplify the power, is used to drive the two-dimensional piston to move in line; Finally, a pair of conversion mechanisms (roller group and spiral track conversion mechanism) are converted into the angular displacement of 2D main spool to control the area of flow valve port. The axial degree of freedom of 2D main spool realizes the function of constant differential pressure. To improve the flow control accuracy of the servo valve, the axial position of the 2D piston is detected by the linear displacement sensor (LVDT), and the signal is transmitted to the controller to realize the closed-loop control. To explore its open-loop characteristics, the mathematical models of torque motor, two-dimensional piston and main spool are established to obtain its open-loop transfer function. Then the AMESIM simulation model is built. To optimize the design of the system, through the dynamic simulation of the system, the influence of key parameters on the dynamic response of the system can be studied. An experimental study is carried out to verify the design feasibility of the servo valve. The experimental results show that under the condition of no-load and full-scale input, the closed-loop delay of the servo valve is 1.84%, the linearity is 2.14%, the step response time is 43 ms, and the dynamic frequency response is 38 Hz. The newly developed 2D3WFFCSV has the advantages of high integration, small size, light weight (801.5 g) and high response and control accuracy. It can replace the constant differential pressure, metering valve and hydraulic servo valve in the aeroengine fuel regulator.

Field programmable gate array implementation of an intelligent soft calibration technique for linear variable differential transformers

Background: Displacement is often used as an indirect indicator for monitoring multiple parameters, i.e. force, velocity, acceleration, and weight, making it an important variable for the measurement and control of processes. Sensors such as Linear Variable Differential Transformers (LVDTs) play a primary role in the design of any displacement measuring instrument. Calibration of an instrument is carried out to produce accurate results from the measuring instrument. Methods: The objective of this study is to calibrate the output of LVDT by designing a signal conditioning circuit so as to extend the linearity range of the sensor to 100% of the full scale input range, and also allows the measurement technique to adapt to variations in the physical parameters of the LVDT, the supply frequency, and the temperature. An optimized neural network is trained to produce linear and adaptive output from the raw data obtained from LVDT. Optimization is achieved by choosing the best neural network algorithm, number of hidden layers and transfer function of neurons which produce the least mean square error. The optimized neural network algorithm is implemented on a Field Programmable Gate Array (FPGA) chip for testing and validation in real life. Results: Experimental results show that the proposed technique was able to extend the linearity of LVDT and make the output adaptive for variations in physical parameters of LVDT, supply frequency and temperature. Conclusions: Accurate measurement of displacement is essential in many process applications, and a good calibration technique is required to produce accurate measurement. The presented calibration technique using optimized neural network algorithms has produced reliable measurements as desired.

Digital Non-Linearity Calibration for ADCs With Redundancy Using a New LUT Approach

This paper presents a novel Look-up Table (LUT) calibration technique for static non-linearity compensation in analog-to-digital converters (ADCs) with digital redundancy, such as Successive Approximation Register (SAR), Algorithmic, Sub-ranging or Pipeline ADCs. The method compensates the performance limitations of the conventional LUT approach in presence of comparison noise and/or non-monotonicity. In these circumstances, the input-output transfer function of a redundant ADC becomes significantly multivalued - that is, different output codes can be achieved for the same input level at different time instants. This behavior is motivated because from sample to sample, in a design with redundancy, the processing signal path is not unique, causing that the error under calibration becomes time-dependent, something which is not contemplated in the conventional calibration model. To deal with this effect, this work proposes a digital low-cost post-processing of the standardized Integral-Non-linearity (INL), which resolves multivalued situations using a direct access to the internal redundant codes. The method improvements are validated by realistic SAR and Pipeline ADC case studies at behavioral level, and by experimental data from an 11-bit 60Msps Pipeline ADC implemented in a 130nm CMOS process. These experimental results show that the proposed calibration achieves an improvement of approximately 1.6 effective bits at full-scale input amplitude.

A 3 mW 6-bit 4 GS/s Subranging ADC With Subrange-Dependent Embedded References

A subranging analog-to-digital converter (ADC) with reference-embedded comparators (RECs) is proposed. By adjusting the bias current and/or body voltage of the REC's input differential pair, the REC offset can be adjusted to a specific voltage equal to a reference voltage referred to henceforth as the embedded reference. For the ADC's coarse stage, RECs with wide-range embedded references are implemented by adjusting the bias currents using current source arrays to cover the full-scale input. By contrast, for the ADC's fine stage, RECs with narrow-range embedded references are implemented by adjusting the body voltage. In addition, the centers of the embedded references in the different ADC subranges are created by current source arrays, which are digitally scaled according to the coarse ADC's output codes. As a result, the reference-voltage-switching network used in conventional subranging ADCs is not required, and hence the speed of the ADC is increased. Moreover, to eliminate the effects of process variation, the bias currents and body voltages in the RECs are calibrated with an auxiliary resistor ladder. After the calibration, the resistor ladder is removed. Consequently, no resistor ladder is used during normal operation, which greatly saves power. A 3 mW 6-bit 4 GS/s REC-based subranging ADC is implemented in 28-nm CMOS technology. With a near Nyquist frequency input, the ADC achieves SNDRs of 31.8 dB and 30.7 dB at 3.6 GS/s and 4 GS/s, respectively. Moreover, at 3.6 GS/s, the ADC has a Walden Figure-of-Merit (FoM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">W</sub> ) of 22.7 fJ/conv-step, which is the best compared with prior state-of-the-art 6-bit high-speed ADCs.

Thermal Analysis Infrastructure in OpenSees for Fire and its Smart Application Interface Towards Natural Fire Modelling

Understanding the fire behaviour in buildings is fundamental and crucial to the practice of structural fire safety design. Traditionally, time-temperature curves associated with a burning rate developed from the “compartment fire framework” are most widely used by structural engineers and applied as a load to the structure. However, the adequacy of homogenous temperature distribution in fully developed fires was questioned by researchers after reviewing the existing fire test data, which suggested a localised burning nature of the fires in relatively large compartments. A groundbreaking travelling fire concept and travelling fire models were then proposed intending to provide an engineering description to this type of natural fire behaviour. The work in this paper was driven by such a trend and first summarises the modelling infrastructure in OpenSees to estimate the thermal response of structural members subjected to various scenario fires, followed by providing a smart application interface to capture the appropriate form of natural fire model through Python-OpenSees framework. The developed modelling infrastructure is validated against uniform and localised fire tests, which are also discussed regarding the smoke effect afterwards. Using the Python-OpenSees infrastructure, a real-scale localised fire test and the Malveira travelling fire test are modelled to demonstrate the modelling strategy. The work as preliminary attempts has shown the necessity of introducing additional variables when describing the natural fire impact, and this framework can be further improved in future by including more fire dynamics research and full-scale fire test input.

A 280 μW, 108 dB DR PPG-Readout IC With Reconfigurable, 2nd-Order, Incremental ΔΣM Front-End for Direct Light-to-Digital Conversion.

This paper reports on a low-power readout IC (ROIC) for high-fidelity recording of the photoplethysmogram (PPG) signal. The system comprises a highly reconfigurable, continuous-time, second-order, incremental delta-sigma modulator (I-ΔΣM) as a light-to-digital converter (LDC), a 2-channel 10b light-emitting diode (LED) driver, and an integrated digital signal processing (DSP) unit. The LDC operation in intermittent conversion phases coupled with digital assistance by the DSP unit allow signal-aware, on-the-fly cancellation of the dc and ambient light-induced components of the photodiode current for more efficient use of the full-scale input range for recording of the small-amplitude, ac, PPG signal. Fabricated in TSMC 0.18μm 1P/6M CMOS, the PPG ROIC exhibits a high dynamic range of 108.2dB and dissipates on average 15.7μW from 1.5V in the LDC and 264μW from 2.5V in one LED (and its driver), while operating at a pulse repetition frequency of 250Hz and 3.2% duty cycling. The overall functionality of the ROIC is also demonstrated by high-fidelity recording of the PPG signal from a human subject fingertip in the presence of both natural light and indoor light sources of 60Hz.

DTMOS Based High Bandwidth Four-Quadrant Analog Multiplier

Analog multiplication circuits are very important block structures which are widely used in analog signal applications. In analog multiplication circuits, low power consumption is expected with wide bandwidth, low nonlinearity and high input range according to supply voltage. In this study, folded Gilbert cell structure was resized using dynamic threshold MOS (DTMOS) transistors and low power consumption and high bandwidth have been obtained. In improver, the bandwidth was obtained at values of 3.63 GHz, temperature variation, total harmonic distortion and intermodulation products of the proposed multiplier were examined. Monte Carlo analysis was performed and error analysis of the dimensioning of the circuit was examined. In summation to the high bandwidth, a low power consumption of 44.5 µW has been achieved and the supply voltage of 0.2 V has been achieved to operate in full-scale input range.

Three-frequency pseudo-random varying spread spectrum method for filterless digital class-D audio amplifiers

This paper presents a novel spread spectrum (SS) method with a pseudo-natural sampling technique for filterless digital class-D audio amplifiers. This method is proposed to reduce the electromagnetic interference (EMI) emissions of amplifiers by lowering the output out-of-band spectral amplitudes around the pulse width modulator carrier frequency and its multiples. The main idea of this method is that the sampling frequency of the modulating signal and the carrier frequency are varied synchronously and randomly among three different values. Since the carrier frequency is variable, the polynomial interpolation Newton–Raphson (PI-NR) algorithm is modified to correct the harmonic distortion caused by uniform-sampling pulse width modulation (UPWM). Based on a field programmable gate array (FPGA), an experimental system is established to analyze the performances of the proposed method and other six reported SS methods. Experimental results show that the proposed method features the lowest total harmonic distortion (THD) of 0.009% with a 6.6 kHz, 0 dBFS (full scale) input, a relatively high signal-to-noise ratio (SNR) of 52.68 dB and a relatively high output out-of-band peak spectral amplitude reduction of 17.75 dB.

12 b 50 MS/s 0.18 μm CMOS SAR ADC based on highly linear C‐R hybrid DAC

A 12 b 50 MS/s successive-approximation register (SAR) ADC with a highly linear C-R hybrid DAC is presented. The proposed DAC significantly reduces the required total number of unit capacitors by processing the upper bits based on a binary-weighted capacitor array and the remaining lower bits based on reference segment voltages, which are obtained from a simple resistor string. The reduced number of unit capacitors enables the use of larger unit capacitance, resulting in improved matching accuracy. In the C-R hybrid DAC, an input range scaling technique, which matches a full-scale input range to the reference voltage range, implements the binary-weighted SAR operation without additional capacitors and reference voltages. The DAC linearity is improved considerably through the process-insensitive capacitor-array layout, which cancels out oxide-gradient errors. The prototype ADC in a 0.18 μm CMOS process demonstrates measured differential and integral non-linearities within 0.71 LSB and 0.85 LSB at 12 b, respectively, with a maximum signal-to-noise-and-distortion ratio and a spurious-free dynamic range of 64.3 and 74.7 dB at 50 MS/s, respectively. The ADC occupies an active die area of 0.17 mm2 and consumes 2.63 mA with a 1.8 V supply voltage.

A General Purpose 1.8-V 12-b 4-MS/s Fully Differential SAR ADC With 7.2-Vpp Input Range in 28-nm FDSOI

This brief describes a differential, 1.8-V, 12-bit 4-MS/s successive approximation register (SAR) analog to digital converter (ADC) with innovative input switch that supports up to 3.6 V inputs using only 1.8-V devices in 28-nm process. This SAR ADC is based on 6–6 split capacitor digital to analog converter architecture with separate sampling capacitor. It features eight pairs of differential input channels. It has a full-scale input range, multiple speed/power modes, and power-down mode for low current consumption. The ADC performs to 11.35 effective number of bits when tested up to 125 C at supply voltages ranging from 1.6 V to 2.0 V and reference voltages ranging from 0.8 V to 2.0 V. Fabricated in a 28-nm fully depleted silicon on insulator process with fringe capacitors, it occupies an area of 0.13 mm2 and has a total dissipation of 960 $ {\mu }\text{A}$ in full speed differential mode and 400 ${\mu }\text{A}$ in low-power single-ended mode. The ADC has been integrated and is in production.

A Continuous-Time Delta-Sigma Modulator Using a Modified Instrumentation Amplifier and Current Reuse DAC for Neural Recording

The use of continuous-time delta-sigma modulators (CTDSM) as a replacement of traditional analog sensor front ends has become an increasingly popular choice. The absence of traditional sensor interface circuits, such as instrumentation amplifiers (IAs), reduces area and power consumption at the cost of robustness offered by these circuits. Selection of the integrator type in the CTDSM is a selection of the ADC properties. This article presents a current feedback CTDSM with high input impedance, wide linear operating range, and large-signal common-mode rejection as a neural recorder front end. We propose the modification of an IA for operation as an integrator in a delta-sigma modulator and the current reuse of the feedback DAC current to bias this integrator stage. Deploying the current reuse technique, the total power consumption of the modulator is reduced by 22%. The ASIC is developed in a 180-nm high-voltage CMOS technology and the analog front end achieves a dynamic range of 90 dB and a total harmonic distortion (THD) of 0.005% when configured for a full-scale input signal of 208 mVpp. A common-mode rejection ratio (CMRR) of 90 dB is measured for a common-mode disturbance of 325 mVpp while the analog power consumption per channel is 23 $\mu \text{W}$ .

A 1-MHz-Bandwidth Gm-C-Based Quadrature Bandpass Sigma-Delta Modulator Achieving −153.7-dBFS/Hz NSD With Background Calibration

This paper presents a fifth-order continuous-time Gm-C-based quadrature bandpass sigma-delta ( $\Delta \Sigma$ ) modulator for Internet-of-Things applications. In the presented $\Delta \Sigma $ modulator, a reconfigurable full-scale input amplitude assists the $\Delta \Sigma $ modulator, achieving a wide dynamic range (DR) and a low-noise floor. A following system-level supply voltage and temperature background tracking technique stabilizes the frequency response of the Gm-C-based quadrature bandpass $\Delta \Sigma $ modulator. Furthermore, the 1.5-bit feedback current DAC employs a PN-based semi-self-swapping logic to relax the matching requirement. The prototype $\Delta \Sigma $ modulator was fabricated in a 180-nm CMOS process with an active area of 0.28 mm2. The $\Delta \Sigma $ modulator achieves a total DR of 93.7 dB with the reconfigurable full-scale input amplitude, resulting in a noise spectral density of −153.7 dBFS/Hz with a bandwidth of 1 MHz. The presented $\Delta \Sigma $ modulator consumes 2.0 mW with a power supply of 1.8 V and a sampling frequency of 32 MHz.

A high accuracy current charge-pump based MDAC for pipelined ADCs

In this paper, a new current charge-pump (CCP) based MDAC is presented. The proposed structure utilizes a new multi-level variable current source (ML-VCS) approach to improve the performance of MDAC in pipelined ADCs. The designed 1.5 bit/stage MDAC is simulated in 0.18 µm scaled CMOS technology with a 2-Vp-p differential full-scale input voltage. The signal-to-noise-and-distortion ratio (SNDR) of the proposed MDAC structure achieves 68 dB at the Nyquist-rate 0.5-Vp-p sinusoidal input with a 2.5 MHz sampling frequency. The power dissipation of MDAC is 7.65 mW under a 1.8-V power supply. Simulation results in HSPICE show that the proposed ML-VCS CCP in MDAC architecture can enhance the accuracy while maintaining the same speed.

MEMS four-terminal variable capacitor for low power capacitive adiabatic logic with high logic state differentiation

This paper presents a novel four-terminal variable capacitor (FTVC) dedicated to the recent concept of low power capacitive adiabatic logic (CAL). This FTVC is based on silicon nano/micro technologies and is intended to achieve adiabatic logic functions with a better efficiency that by using field effect transistor (FET). The proposed FTVC consists of two capacitors mechanically coupled and electrically isolated, where a comb-drive input capacitor controls a gap-closing capacitor at the output. To fully implement the adiabatic combinational logic, we propose two types of variable capacitors: a positive variable capacitor (PVC) where the output capacitance value increases with the input voltage, and a negative variable capacitance (NVC) where the output capacitance value decreases when the input voltage increases. A compact and accurate electromechanical model has been developed. The electromechanical simulations demonstrate the ability of the proposed FTVC devices for CAL, with improved features such as high logic states differentiation larger than 50% of the full-scale input signal and cascability of both buffers and inverters. Based on the presented analysis, 89% of the total injected energy in the device can be recovered, the remaining energy being dissipated through mechanical damping. During one cycle of operation, a buffer gate of 10 × 2.5 µm2 dissipates only 0.9fJ.

A low-power rail-to-rail input-range linear delay element circuit

Delay elements are one of the key components in many time-domain circuits such as time-based analog-to-digital converters. In this paper, a new rail-to-rail current-starved delay element is proposed which not only presents good linearity for the voltage-delay curve over the input range of ground to supply voltage, but also it consumes a dynamic power only during the transition times without consuming any static power. The proposed delay element is designed and simulated in a 0.13-µm CMOS technology with a supply voltage of 1.2V. Post-layout simulation results demonstrate that the proposed circuit has a linear voltage-delay transfer function with a voltage-to-time gain of −1.33ps/mV. Moreover, when samples of a full-scale sin-wave input signal are applied to the proposed circuit with a clock frequency of 100MHz, the power consumption is 30µW, and signal-to-noise-and-distortion ratio (SNDR) of the output delay times is 30.4dB, making it suitable for use in a time-based analog-to-digital converter with up to 5-bit resolution.

A 200-nW 7.6-ENOB 10-KS/s SAR ADC in 90-nm CMOS for Portable Biomedical Applications

This paper presents an 8-bit low-power clock gated successive approximation analog to digital converter (SA-ADC) using D-flip flop (D-FF) unit for biomedical applications. The architecture of the proposed SA-ADC is implemented using the sample and hold (S/H) circuit which is based on a sampling transistor with dummy switch, double-tail dynamic latched comparator, the traditional binary weighted capacitor array single ended DAC and a modified clock gated successive approximation register (SAR) controller logic. The SAR controller is implemented using D-FF. The layout and extraction of the proposed low-power clock gated SA-ADC using D-FF unit are done using L-edit and simulated using 90nm CMOS technology file on LT-spice-IV. According to the simulation results, the low-power clock gated SA-ADC using D-FF unit consumes 200nW from 1V power supply without additional calibration or analog circuits. It has signal-to-noise ratio (SNR) of 53.8dB, peak spurious-free dynamic range (SFDR) of 54.2dB, and a signal-to-noise-and distortion ratio (SNDR) of 48dB for a 250Hz full scale input sine wave. It has also an effective number of bits (ENOB) of 7.6-bits, and a figure of merit (FOM2) of 0.1 pJ/Conversion-step. It achieves +0.34/−0.3 and +0.79/−0.58 of Differential non-linearity (DNL) and integral non-linearity (INL) errors respectively. Furthermore, the low-power clock gated SA-ADC using D-FF unit consumes 88.76nW from 0.85V power supply without additional calibration or analog circuits. With 0.85V supply voltage, it has SNR, SFDR and SNDR of 54.6dB, 39.19dB and 37.92dB respectively for the same input sinewave. It achieves ENOB of 6-bits with (FOM2) of 0.13 pJ/Conversion-step. It has DNL and INL of +0.38/−0.28 LSB and +0.9/−0.85 LSB respectively. The digitized of real recorded beta EEG signal is precisely reconstructed by the proposed SA-ADC.

A Low-Power TDC-Configured Logarithmic Resistance Sensor for MLC PCM Readout

This paper proposes a low-power logarithmic resistance sensor for multi-level cell phase-change memory readout. The proposed sensor is composed of a resistance-to-current converter (R2I) and a current-to-digital converter (I2D). A simple bleeding current source pair added to the R2I enhances the current settling speed and the sensing accuracy. The two-step I2D with a time-to-digital converter-configured fine ADC could be designed with low-power consumption and small size owing to the time-reference generator that is shared by multiple channels and incorporates interpolation and size-scaling techniques. The total conversion time of the readout sensor, including the R2I conversion, is 100 ns, and the power consumption of a single-channel readout sensor is 60 μW under a 1.2 V supply. The ratio of the minimum decision step size to the full scale input current of the I2D corresponds to that of a conventional 9.6-b linear ADC. The prototype sensor is composed of 14-channels sharing a single time-reference generator, where each narrow single channel occupies 19 μm × 590 μm in a 65-nm CMOS process.