Full-scale Input Research Articles

A 10-bit 200-MS/s Zero-Crossing-Based Pipeline ADC in 0.13-$\mu $ m CMOS Technology

This brief presents a zero-crossing-based pipeline analog-to-digital converter (ADC) architecture that can effectively reduce hardware complexity and power consumption for high-speed ADCs. The ADC uses only simple open-loop amplifiers for residue amplification. Using modified sliding interpolation and subranging techniques, the number of amplifiers is reduced by 60%. A 10-bit 200-MS/s ADC, employing the architecture and other techniques, such as double sampling, digital error correction, and source degeneration, is fabricated in 0.13- $\mu $ m CMOS process and occupies a die area of 0.7 $\mathrm{mm}^{2}$ . The differential and integral nonlinearity of the ADC are less than 0.83/−0.47 and 1.05/−0.7 LSB, respectively. With a 1.5-MHz full-scale input, the ADC achieves 56.5-dB signal-to-noise plus distortion ratio, 71.8-dB spurious free dynamic range, and 9.1 effective number of bits at full sampling rate while dissipating 38 mW from a 1.2-V supply.

Energy‐efficient successive‐approximation‐register based capacitive interface for pressure sensors

A novel energy-efficient 8 bit 2.78 kS/s capacitance-to-digital converter (CDC) interface for capacitive pressure sensors is presented. A new direct-capacitance-comparison technique (DCCT) is proposed and employed together with a successive approximation register (SAR) algorithm to resolve the sensor capacitance by, directly, comparing it with an on-chip binary-weighted capacitive digital-to-analogue converter (DAC) array. An offset DAC array compensates for the sensor rest and parasitic capacitances, accordingly, the interface gives a dynamically zoomed digital-output code that corresponds only to the sensor capacitance change. The full-scale input capacitance of the CDC is easily adjustable to interface to a wide range of sensors. The proposed 8 bit SAR-based CDC is designed and simulated using 0.18 μm standard CMOS technology. The CDC exhibits a capacitance sensing range from 4 to 6 pF, provides a resolution and linearity of 7.26 and 8.2 bit, respectively. It achieves a figure-of-merit of 1.8 pJ/step at 1.4 V supply and 36 μs conversion time. Compared with the state-of-the-art implementations with similar performance.

A Practically Validated Intelligent Calibration Technique using Optimized ANN for Ultrasonic Flow meter

Design of an intelligent flow measurement technique by ultrasonic transducers using an Optimized Artificial Neural Network (OANN) is discussed in this paper. The objectives of the present work are (i) to extend the linearity range of flow measurement to 100% of full scale input range, (ii) to make the flow measurement technique adaptive to variations in (a) pipe diameter, (b) liquid density, (c) liquid temperature, and (iii) to achieve objectives (i) and (ii) by using an optimized artificial neural network. The output of an ultrasonic transducer is frequency. It is converted to voltage by using a suitable data conversion circuit. A suitable optimal ANN is added, in place of conventional calibration circuit, in cascade to data conversion circuit. ANN is trained, and tested with simulated data considering various values of pipe diameter, liquid density, and liquid temperature. The proposed technique is then subjected to practical data for validation. Results show that the proposed technique has fulfilled the desired objectives.

Efficient Broadband Current-Mode Adder- Quantizer Design for Continuous-Time Sigma–Delta Modulators

A 3-bit current-mode flash quantizer with current summing stage in a commercial 90-nm CMOS technology is presented. The topology is intended for low-power feed-forward continuous-time sigma–delta modulators. Current summation is realized using a common-gate structure. Replicas of the input signal current are compared with the reference currents through high-impedance nodes that ease the signal quantization. The comparison stage employs reset switches to enable fast comparisons. The proposed approach involves zero crossing comparators, and it employs current references instead of voltage references that demand a power-hungry resistive ladder. Results show that the proposed current-mode approach is faster than the conventional voltage-mode flash approach, and it requires a smaller input capacitance while consuming 53% less power. A 3-bit prototype design has a measured effective number of bits over 2.6 bits up to 2-GHz clock frequency with 10-MHz full-scale input signal. At 1.48-GHz clock frequency, the static differential nonlinearity (DNL) and integral nonlinearity (INL) errors are within −0.206 least significant bit (LSB) and 0.206 LSB, respectively. The proposed current-mode flash analog-to-digital converter (ADC) core dissipates 3.34-mW analog power from a 1.2 V supply while operating at 1.48 GHz. The core area of the ADC including the biasing circuitry is 0.0276 $\mathrm{mm}^{\mathrm {\mathbf {2}}}$ .

A Practically Validated Adaptive Calibration Technique using Optimized Artificial Neural Network for Level Measurement by Capacitance Level Sensor

Design of an adaptive calibration technique using an optimized artificial neural network for liquid-level measurement is discussed in this paper. The objective of the present work is to design and validate an adaptive calibration technique so as (1) to extend the linearity range of measurement to 100% of full-scale input range and (2) to make the measurement technique adaptive of variations in tank diameter, permittivity of liquid, liquid temperature, and to achieve objectives (1) and (2) using an optimized neural network. An optimized artificial neural network is a network having least possible number of hidden layers to achieve minimum mean square error between outputs and targets by comparing various algorithms, schemes, and transfer functions of neuron. The output of capacitance level sensor is capacitance. A data conversion unit is used to convert it to voltage. A suitable optimized artificial neural network is designed and used in place of conventional calibration circuit. The proposed technique is tested with simulated data and validated with practical data. Results show that proposed technique has fulfilled the set objectives.

Power and Bandwidth Scalable 10-b 30-MS/s SAR ADC

A successive approximation register (SAR) analog-to-digital converter (ADC) with a fixed antialiasing frequency that allows tradeoffs between power consumption and signal bandwidth is presented. The ADC, without increasing hardware complexity, can reduce power consumption significantly by skipping MSB conversions when they are unnecessary. By sampling and converting only the difference between two successive input samples, DAC capacitor switching power reduces as oversampling ratio (OSR) increases. For OSR = 1, a 1.2-V 10-b 30-MS/s ADC fabricated in 0.18- $\mu $ m CMOS process consumes $980~\mu $ W and achieves signal-to-noise-plus-distortion ratio (SNDR) and spurios-free dynamic range (SFDR) of 56.2 and 68.6 dB, respectively, resulting in a figure-of-merit (FOM) of 67-fJ/conversion-step for a 14.1-MHz full-scale input. For OSR = 16, the ADC dissipating $231~\mu $ W from a 1.2-V supply, achieves a FOM of 42.7-fJ/conversion-step for a 1.125-MHz full-scale input.

Design of a low power 10 bit 300 ksps multi-channel SAR ADC for wireless sensor network applications**Project supported by the National Natural Science Foundation of China (No. 61107025) and the Key Innovation Team Project of Zhejiang Province (No. 2010R50010).

This paper presents a low power 10 bit 300 ksps successive approximation register analog-to-digital converter (SAR ADC) which is applied in wireless sensor network (WSN) applications. A single ended energy-saving split capacitor DAC array and a latch comparator with a rail to rail input stage are utilized to implement the ADC, which can reduce power dissipation while expanding the full scale input range and improve the signal-to-noise ratio (SNR). For power optimization the supply voltage of the SAR ADC is designed to be as low as 2 V. Four analog input channels are designed which make the ADC more suitable for WSN applications. The prototype circuit is fabricated using 3.3 V, 0.35 μm 2P4M CMOS technology and occupies an active chip area of 1.23 mm2. The test results show that the power dissipation is only 200 μW at a 2 V power supply and a sampling rate of 166 ksps. The calculated SNR is 58.25 dB, the ENOB is 9.38 bit and the FOM is 4.95 pJ/conversion-step.

A Practically Validated Intelligent Calibration Circuit Using Optimized ANN for Flow Measurement by Venturi

Design of an intelligent flow measurement technique using venturi flow meter is reported in this paper. The objectives of the present work are: (1) to extend the linearity range of measurement to 100 % of full scale input range, (2) to make the measurement technique adaptive to variations in discharge coefficient, diameter ratio of venturi nozzle and pipe (β), liquid density, and liquid temperature, and (3) to achieve the objectives (1) and (2) using an optimized neural network. The output of venturi flow meter is differential pressure. It is converted to voltage by using a suitable data conversion unit. A suitable optimized artificial neural network (ANN) is added, in place of conventional calibration circuit. ANN is trained, tested with simulated data considering variations in discharge coefficient, diameter ratio between venturi nozzle and pipe, liquid density, and liquid temperature. The proposed technique is then subjected to practical data for validation. Results show that the proposed technique has fulfilled the objectives.

A 10 bit SAR ADC With Data-Dependent Energy Reduction Using LSB-First Successive Approximation

This paper presents a successive approximation (SA) algorithm called LSB-first SA and a corresponding 10 bit ADC implementation. The energy per conversion and number of bitcycles per conversion used by this algorithm both scale logarithmically with the activity of the input signal, such that an N-bit conversion uses between 2 and 2N+1 bitcycles, compared to N for conventional binary SA. This algorithm reduces ADC power consumption when sampling signals with low mean activity. The ADC is implemented in a 0.18 μm CMOS process. With a 0.6 V supply, the maximum sample rate, leakage power, and ENOB are 16 kHz, 0.58 nW, and 9.73 b, averaged over 10 test chips. The DNL and INL are bounded at 0.09 and 0.22 LSBs. Given a DC input, the ADC achieves its best-case FoM of 3.5 fJ/conversion-step. Given a fullscale Nyquist sinusoid input, the ADC has its worst-case FoM of 20 fJ/conversion-step. The supply voltage can be increased to 1.0 V to reach a sample rate of 450 kHz, or decreased to 0.5 V to achieve a 2.9-17 fJ/conversion-step FoM range.

A 1-V, 330-nW, 6-Bit Current-Mode Logarithmic Cyclic ADC for ISFET-Based $$p\!H$$ p H Digital Readout System

This paper describes the design and implementation of a low-power current-mode logarithmic analog-to-digital converter (ADC) for an ISFET-based $$p\!H$$pH digital readout system. The system comprises a front-end ISFET-based $$p\!H$$pH readout circuit and a succeeding logarithmic ADC to produce a digital output signal which is linearly related to the input $$p\!H$$pH variation. The front-end $$p\!H$$pH readout circuit is realized using a subthreshold ISFET/REFET differential pair with a current-mode translinear multiplier/divider circuit. The logarithmic ADC is realized using the cyclic architecture and current-mode circuit techniques to achieve low power dissipation. High-accuracy current sample-and-hold circuit based on the regulated-cascode switched-current memory cell and low-power high-resolution current comparator are proposed for the ADC realization. All circuits were designed to operate with a single 1-V power supply voltage, and were simulated with process parameters from a 0.18-$$\mu $$μm CMOS technology. The power dissipation of the front-end $$p\!H$$pH readout circuit and the logarithmic ADC is 20 and 330 nW, respectively. The front-end $$p\!H$$pH readout circuit can produce an output current range of 0.1---300 nA which is logarithmically corresponded to the input $$p\!H$$pH range of 4---10. The logarithmic ADC operates with 1-kS/s sampling rate and achieves the integral nonlinearity error of $$\pm 0.8$$±0.8 LSB, the effective number of bits of 5.95, and 37.6-dB of signal-to-noise-distortion ratio with 100-nA full-scale input range.

Three-dimensional urban acoustic simulations and scale-model measurements over real-life topography.

Comparisons of finite-difference time-domain sound propagation simulations over real-life urban topography with scale-model experimental measurements are performed. A 1:100 scale model for the measurements and full-scale input geometry for the simulations are created by using digital geographic datasets. The sound pressure levels obtained by the measurements and simulations resulted in approximately 2 dB of root mean square error in the 125 and 250 Hz octave bands, and 4 dB in 500 Hz. Visualizations of a low-frequency sound propagation case by the measurement and simulation clearly show the wave phenomena caused by buildings and natural terrain.

An in-probe receiver amplifier with 3 dB noise figure and 50 dB dynamic range for medical ultrasound imaging using CMUTs

This paper presents the design and measurements of an in-probe receiver amplifier for ultrasound imaging applications using a capacitive micromachined ultrasonic transducer (CMUT). In such applications, the noise and the dynamic range play very important roles, as the former dictates the minimum input signal level and the latter defines the maximum input signal level that can be applied to a system. This work concentrates on both of these specifications. The amplifier consists of a transimpedance amplifier followed by a voltage gain stage implemented using a current feedback amplifier. It is designed and fabricated using a 180 nm CMOS process. A noise figure of 3 dB is measured for a CMUT model with 10---30 MHz frequency range. The amplifier shows a dynamic range of 50 dB with 0.8 % total harmonic distortion for the full scale input current of 7 µA peak-to-peak.

A 1. 5-V, 10-bit, 200-MS/s CMOS Pipeline Analog-to-Digital Converter

Analog-to-digital converters (ADCs) are required in almost all communication and signal processing applications. This paper describes a 1.5-v, 10-bit, 200-Msample/s pipeline analog-todigital converter in 0.18-μm CMOS technology. The entire circuit architecture is built with a modular approach consisting of identical units organized into an easily expandable pipeline chain. The converter uses ten stage pipelined architecture with fully differential analog circuits, with a full-scale sinusoidal input at 10 MHz’s A special focus is made on pipelined ADC for its superior performance in terms of speed and resolution. General Terms Op-amp, Flip-flop, Adders,

A 10-b 50-MSPS Low Power Pipeline ADC for Ultra-High Energy Cosmic Rays Detection

The upgrade of the Pierre Auger Observatory required a larger number of detectors that implies a dramatic increase of the power consumption. As the analog-to-digital converter (ADC) is the most critical circuit block, an integrated solution is here proposed. A 10 b 50-MSps 5-stage pipeline ADC is implemented in 65 nm digital CMOS. It achieves 50.3 dB signal-to-noise and distortion ratio (SNDR), 52.3 dB signal-to-noise ratio (SNR), 59.2 dB spurious free dynamic range (SFDR) for a full-scale input sinewave at Nyquist frequency. The ADC features 12 mW power consumption from a 1.2 V supply, while occupying 0.8 mm2 die area.

Resolution upgrade toward 6-bit optical quantization using power-to-wavelength conversion for photonic analog-to-digital conversion

We demonstrate a resolution upgrade toward 6 bit optical quantization using a power-to-wavelength conversion without an increment of system parallelism. Expansion of a full-scale input range is employed in conjunction with reduction of a quantization step size with keeping a sampling-rate transparency characteristic over several 100 sGS/s. The effective number of bits is estimated to 5.74 bit, and the integral nonlinearity error and differential nonlinearity error are estimated to less than 1 least significant bit.

A Multi-Fork Z-Axis Quartz Micromachined Gyroscope

A novel multi-fork z-axis gyroscope is presented in this paper. Different from traditional quartz gyroscopes, the lateral electrodes of the sense beam can be arranged in simple patterns; as a result, the fabrication is simplified. High sensitivity is achieved by the multi-fork design. The working principles are introduced, while the finite element method (FEM) is used to simulate the modal and sensitivity. A quartz fork is fabricated, and a prototype is assembled. Impedance testing shows that the drive frequency and sense frequency are similar to the simulations, and the quality factor is approximately 10,000 in air. The scale factor is measured to be 18.134 mV/(°/s) and the nonlinearity is 0.40% in a full-scale input range of ±250 °/s.

An 11b Pipeline ADC With Parallel-Sampling Technique for Converting Multi-Carrier Signals

This paper presents a parallel sampling technique for analog-to-digital converters (ADCs) to convert multi-carrier signals efficiently by exploiting the statistical properties of these signals. With this technique, the input signal power of an ADC can be boosted without getting excessive clipping distortion and the ADC can have a higher resolution over the critical small amplitude region. Hence the overall signal to noise and clipping distortion ratio is improved. This technique allows reducing power dissipation and area in comparison to conventional solutions for converting multi-carrier signals. As an example, an 11b switched-capacitor pipeline ADC with the parallel sampling technique applied to its first stage is implemented in CMOS 65 nm technology. It achieves a full-scale input signal range of 2 V differentially with a 1.2 V supply voltage. Simulations show an improvement of more than 5 dB in signal-to-noise-and-clipping-distortion ratio (SNCDR) and around 8 dB in dynamic range (DR) compared to a conventional 11b ADC for converting multi-carrier signals and achieve a comparable SNCDR and noise power ratio (NPR) as a conventional 12b pipeline for converting multi-carrier signals with less than half the power and area.

Optimal Design for Delta–Sigma Modulators With Root Loci Inside Unit Circle

Single-stage high-order delta-sigma modulators (DSMs) designed by methods with root loci inside the unit circle (RLiUC) can operate stably with full-scale input. The previously published RLiUC method uses a conservative approach to design the loop filter's transfer function H(z) of a DSM, thus resulting in a modest SNR. In this brief, the pole-zero locations of H(z) are optimized to maximize the stable input range while minimizing SNR reduction. Accordingly, optimal third- and fourth-order RLiUC DSMs are designed, and a systematic method for orders higher than 4 is developed. The considerations for the optimal design are the in-band noise attenuation and out-of-band gain of RLiUC DSMs. With an oversampling ratio of 32 and a quantizer bit number of 6, the optimized fourth-order RLiUC DSM achieves a peak SNR of 109 dB. Compared with the previously published result, the SNR is improved by 20 dB. To demonstrate the advantage of RLiUC DSMs, an application example for a class-D amplifier is used. With the RLiUC DSM, the achieved low-distortion output power of class-D amplifiers can be maximized.

A 330 MHz 11 bit 26.4 mW CMOS Low-Hold-Pedestal Fully Differential Sample-and-Hold Circuit

A new technique for realizing a very-high-speed low-power low-voltage fully differential CMOS sample-and-hold circuit with low hold pedestal is presented. To achieve high sampling linearity the circuit utilizes linearized input switches. The fully differential design relaxes the trade-off between sampling speed and the sampling precision. The circuit design of major building blocks is described in detail. A prototype circuit in a 0.35-μm CMOS process is designed and experimental results are presented. The sample-and-hold circuit operates up to 330 MHz of sampling frequency with less than −68.3 dB of total harmonic distortion, corresponding to 11 bits for an input 80.24 MHz sinusoidal amplitude of 1.2V pp at a 3 V supply. This total harmonic distortion measurement reflects the held values as well as the tracking components of the output waveform. In these conditions, a differential hold pedestal of less than 0.8 mV, 0.8 ns acquisition time at 1.2 V step input, and 1.2V pp full-scale differential input range are achieved. The circuit dissipates 26.4 mW with a 3 V power supply.

LMS-Based Noise Leakage Calibration of Cascaded Continuous-Time $\Delta\Sigma$ Modulators

In cascaded ΔΣ modulators (DSMs), the quantization noise of the earlier stage leaks to the output unless completely cancelled by the digital noise cancellation filter (NCF). The noise leakage is worse in the continuous-time (CT) implementation due to the poorly controlled time constant of the analog loop filter. A parameter-based continuous-time to discrete-time transform is developed to get an exact digital NCF, and the analog filter time constant is calibrated to match with the digital NCF. A binary pulse tone is injected into the quantizer to detect the filter time-constant error, and eliminated by zero-forcing its residual power based on the adaptive least-mean-square (LMS) algorithm. A 2-1-1 cascaded CT-DSM prototype in 0.18-μm CMOS demonstrates that the spectral density of the leaked noise is lower than 10 nV/?Hz after the capacitors in the Gm-C loop filters are trimmed with 1.1% step. With a 1-Vpp full-scale input, it achieves a dynamic range of 68 dB within 18-MHz bandwidth at an over-sampling ratio of 10. The analog core and the digital logic occupy 1.27 mm2,and consume 230 mW at 1.8 V.