Power and Bandwidth Scalable 10-b 30-MS/s SAR ADC

Abstract

A successive approximation register (SAR) analog-to-digital converter (ADC) with a fixed antialiasing frequency that allows tradeoffs between power consumption and signal bandwidth is presented. The ADC, without increasing hardware complexity, can reduce power consumption significantly by skipping MSB conversions when they are unnecessary. By sampling and converting only the difference between two successive input samples, DAC capacitor switching power reduces as oversampling ratio (OSR) increases. For OSR = 1, a 1.2-V 10-b 30-MS/s ADC fabricated in 0.18- $\mu $ m CMOS process consumes $980~\mu $ W and achieves signal-to-noise-plus-distortion ratio (SNDR) and spurios-free dynamic range (SFDR) of 56.2 and 68.6 dB, respectively, resulting in a figure-of-merit (FOM) of 67-fJ/conversion-step for a 14.1-MHz full-scale input. For OSR = 16, the ADC dissipating $231~\mu $ W from a 1.2-V supply, achieves a FOM of 42.7-fJ/conversion-step for a 1.125-MHz full-scale input.