Full Adder Research Articles

Design a novel 1-bit full adder with hybrid logic for full-swing, area-efficiency and high-speed

Design a novel 1-bit full adder with hybrid logic for full-swing, area-efficiency and high-speed

High Performance and Scalable Hybrid Memristor-CMOS Based Full Adder

The field of digital computation has recently drawn attention to the memristor as a circuit element due to its nanoscale structure and integration capabilities with MOSFETs. As a result, there have been various attempts to use hybrid memristor-CMOS circuits to rebuild the fundamental digital building blocks. This paper presents a new hybrid memristor-CMOS-based full adder (HMC-FA) design. This design aims to minimize propagation delay, power dissipation, power delay product (PDP), and device count (memristor and transistor count). The proposed design is implemented in Cadence Virtuoso toolset utilizing CMOS gpdk 180nm process technology parameters. Comparative investigation demonstrates that the proposed HMC-FA improves PDP by 71.95%−99.83%. The proposed circuit is designed with 12 transistors and 6 memristors. The proposed design consumes 8.24µW of total power while the propagation delay is 112.71ps at 1.8V supply voltage. To verify the scalability of the HMC-FA cell, full adders up to 32-bit word length are designed, and performance parameters are evaluated at 1.8V, 100MHz supply voltage.

PERFORMANCE ANALYSIS OF OPTICAL PARALLEL FULL ADDER USING ARTIFICIAL NEURAL NETWORK

A verbal exchange today wishes for quick operational progress. This can be accomplished by replacing devices that are primarily concerned with commutation and logic with photon-based systems instead of the usual data service, the electron. The basic building blocks of superior frames are called gates. With the aid of these gates, various logical and mathematical operations can be performed. All-optical arithmetical and logical processes are eagerly expected in high-speed dialogue frameworks. In this chapter, we’ve introduced parallel models for adding two binary digits that are based on Sagnac gates with help from semiconductor optical amplifiers (SOA) and terahertz optical asymmetric demultiplexers (TOAD). We created a Full adder that works in parallel using only two TOADs as total switches. Using artificial neural networks (ANN), we have created a model of this circuit that is equivalent. Utilizing ANN, this circuit design has been validated. This optical circuit is now capable of synthesizing light as an input and successfully structuring the aspiration output in addition to speeding up calculation. This parallel circuit’s biggest advantage is that it doesn’t need synchronization for distinct inputs. An ANN model was used to analyze this circuit’s performance in detail.

Improved Arithmetic Performance by Combining Stateful and Non‐Stateful Logic in Resistive Random Access Memory 1T–1R Crossbars

Computing‐in‐memory (CIM) is a promising approach for overcoming the memory‐wall problem in conventional von‐Neumann architectures. This is done by performing certain computation tasks directly in the storage subsystem without transferring data between storage and processing units. Stateful and non‐stateful CIM concepts are recently attracting lots of interest, which are demonstrated as logical complete, energy efficient, and compatible with dense crossbar structures. However, sneak‐path currents in passive resistive random access memory (RRAM) crossbars degrade the operation reliability and require the usage of active 1 Transistor–1 Resistance (1T‐1R) bitcell designs. In this article, the arithmetic performance and reliability are investigated based on experimental measurements and variability‐aware circuit simulations. Herein, it is aimed for the evaluation of logic operations specifically with fully integrated 1T–1R crossbar devices. Based on these operations, an N‐bit full adder with optimized energy consumption and latency is demonstrated by combining stateful and non‐stateful CIM logic styles with regard to the specific conditions in active 1T–1R RRAM crossbars.

Design and implementation of high-performance 20-T hybrid full adder circuit

Design and implementation of high-performance 20-T hybrid full adder circuit

Speed, Power and Area Optimized Monotonic Asynchronous Array Multipliers

Multiplication is a fundamental arithmetic operation in electronic processing units such as microprocessors and digital signal processors as it plays an important role in various computational tasks and applications. There exist many designs of synchronous multipliers in the literature. However, in the domain of Input–Output Mode (IOM) asynchronous design, there is relatively less published research on multipliers. Some existing works have considered quasi-delay-insensitive (QDI) asynchronous implementations of multipliers. However, the QDI asynchronous design paradigm, in general, is not area- and speed-efficient. This article presents an efficient alternative implementation of IOM asynchronous multipliers based on the concept of monotonic Boolean networks. The array multiplier architecture has been considered for demonstrating the usefulness of our proposition. The building blocks of the multiplier, such as the partial product generator, half adder, and full adder, were implemented monotonically. The popular dual-rail encoding scheme was considered for encoding the multiplier inputs and outputs, and four-phase return-to-zero handshaking (RZH) and return-to-one handshaking (ROH) were separately considered for communication. Compared to the best of the existing QDI asynchronous array multipliers, the proposed monotonic asynchronous array multiplier achieves the following reductions in design metrics: (i) a 40.1% (44.3%) reduction in cycle time (which is the asynchronous equivalent of synchronous clock timing), a 37.7% (37.7%) reduction in area, and a 4% (4.5%) reduction in power for 4 × 4 multiplication corresponding to RZH (ROH), and (ii) a 58.1% (60.2%) reduction in cycle time, a 45.2% (45.2%) reduction in area, and a 10.3% (11%) reduction in power for 8 × 8 multiplication corresponding to RZH (ROH). The multipliers were implemented using a 28 nm CMOS process technology.

Power Efficient Implementation of ECC Using LCSLA Based Dual Field Vedic Multiplier

The Elliptic Curve Cryptographic (ECC) technique is employed for security standards such as Security Key Management (SKM), digital signature, data authentication and so on. The ECC technique is capable of sequential and parallel mode processes through a unified design. It is used for both equally binary fields and prime fields of cryptosystems. The DMM structure has been developed using CSA. This adder requires a greater amount of Full Adder circuits, which occupy more area. To overcome this problem, this paper discusses four different methods, such as DMM-Optimized Carry Look Ahead Adder, DMM-Optimized Carry Bypass Adder, DMM-Look up Table Carry Select Adder, and Dual Field Vedic Multiplier – LCSLA, which is used to increase the performance of the ECC. The parameters like power utilization, time delay information, and hardware area overhead are analyzed and compared with existing methods. Among those four methods, the DVM-LCSLA method gave better results in FPGA and ASIC performances.

Energy-efficient and fast IMPLY-based approximate full adder applying NAND gates for image processing

Today’s processing applications require frequent and energy-consuming data transfers between memory and processing elements. Reducing the dimensions of Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) brings essential problems. Therefore, applying emerging technologies should be considered as a solution. As a crossbar array compatible technology, memristors can play the computing and memory device roles. Therefore, it is suitable for In-Memory Computing (IMC). The issue of changing the computation method to achieve higher efficiency can also be considered. Today, approximate computing is of great interest for error-tolerant applications. These two concepts are applied, and an approximate serial full adder based on the Material Implication (IMPLY) method is introduced. The proposed Serial Approximate Full Adder using NAND gates (SAFAN) reduces the number of steps and energy consumption by up to 30% and 26% compared to approximate ones, 70% and 68% compared to exact ones, respectively. The error analysis results show that the accuracy decreases to a reasonable level by applying the SAFAN to the least significant bits (LSBs) of an approximate 8-bit adder. Image analysis criteria evaluated the functionality of the SAFAN in image processing applications, and the results showed the suitable performance of the SAFAN in error-tolerant applications.

A new design of a digital filter for an efficient field programmable gate array using quantum dot technology

Digital filtering algorithms are most frequently used to implement generic-based Field-programmable gate arrays (FPGAs) chips, which are used for higher sampling rates. In the filtering structure, delay and occupied areas play a vital role. Since the existing structures suffered from shortcomings such as high delay and high occupied area, implementing a high-performance digital filter circuit with high speed and low occupied area based on unique technology can significantly improve the performance of whole FPGA structures. One of the best technologies to implement this vital structure to solve these shortcomings is quantum-dot cellular automata (QCA) technology. This paper presents several new efficient full adders for digital filter applications based on quantum technology, including a multiplier, AND gate, and accumulator. The QCADesigner 2.0.3 tool is used to create and validate the suggested designs. According to the results, all designed circuits have simple structures with few quantum cells, low area, and low latency.

Efficient approximate multipliers utilizing compact and low-power compressors for error-resilient applications

Approximate computing is one of the promising techniques in error-resilient applications to overcome high-density integration challenges, such as energy consumption and performance. Multipliers constitute a significant portion of computer arithmetic units, leading to considerable energy and time consumption. In this paper, we propose low-power and compact approximate compressors for composing approximate Dadda multiplier structures, including compressors, half adders, and full adders, which utilize three-phase partial product compression: truncated, approximation, and exact columns. In approximate columns, we consider approximate compressors derived from the truth table of the exact 4:2 compressor and simplified K-map entries based on the probability of each combination of inputs. An error-correcting module (ECM) is designed to distinguish specific cases and reduce the error metrics. All circuits were simulated using ModelSim and then synthesized using Design Compiler with the 15 nm FinFET technology. When compared to state-of-the-art works, our multipliers exhibit approximately 30%, 43%, and 10% reductions in power, area, and delay, respectively. To evaluate their functionality, we conducted image multiplication and implemented a simple multi-layer perceptron (MLP) neural network using the modified National Institute of Standards and Technology (MNIST) dataset in MATLAB with 0.998 mean structural similarity index metric (MSSIM), 51 dB peak-signal noise ratio (PSNR), and 95% classification accuracy.

FPGA Implementation of High-Performance Truncated Rounding based Approximate Multiplier with High-Level Synchronous XOR-MUX Full Adder

In research and development, the most emerging field in digital signal processing and image processing is rounded-based approximated signed and unsigned multipliers. In the present research, we propose some cutting-edge, Preformation, and logic simplification technology connected to processing the Discrete cosine transform (DCT) and Discrete wavelet transform (DWT) images for sharpening. This technology will yield a truncated shifter incorporated with logical XOR-MUX Full adder techniques. A reliable and cost-effective approximate signed and unsigned multiplier was created for the rounding method. While this more advanced technology includes many approximate multipliers, it sacrifices the ability to find the closest integer of a rounded value when combining signed and unsigned capabilities, resulting in higher absolute errors than other approximate multipliers based on rounding. This proposed work will introduce a novel method of Truncated Shifter Rounding-based Approximate Multiplier integrated with a High-Level Synchronous XOR-MUX Full Adder design to minimize the number of logic gates and power consumption in the multiplier architecture. The Truncated RoBA (Rounding-based Approximate Multiplier) with XOR MUX Full Adder will reduce the logic size in the shifter and the arithmetic circuit. The work will modify this rounding-based approximate multiplier to minimize area, delay, and power consumption. This proposed architecture will be integrated with two fundamental changes: firstly, its Barrel shifter method will be replaced with a truncated shifter multiplier with XOR MUX Full Adder, and secondly, the parallel prefix Brent Kung adder will be replaced with a carrying-save adder with XOR MUX Full Adder. Finally, this architecture was designed using Verilog-HDL and synthesized using the Xilinx Vertex-5 FPGA family, targeting the device Xc7Vx485tFFg1157-1. It resulted in a reduction of area LUT (34%), power (1%), delay (32%), and error analysis (75%) when compared to the existing RoBA.

Utilizing a Novel Universal Quantum Gate in the Design of Fault-Tolerant Architecture

In nano communication, fault-tolerant networks play a crucial role in error control. A significant practical challenge for nanocircuits is their ability to transmit information over networks to different endpoints. Fault-tolerant and reversible circuits have control error problems. The advantage of a quantum gate-based architecture is that it prevents heat loss, and it has been extensively researched. In this article, we have developed reversible multiplexers (mux's), half-adder (HA), and full-adder (FA) and latches that are fault-tolerant by making use of new gate and implementing them on the IBM Qiskit platform. A power-efficient and fault-tolerant mux's and latches is proposed that uses reversible gates to preserve parity. Multiplexer kinds such as 2:1, 4:1, and n:1 is covered in depth by the new Parity Preserving Multiplexer (PPM) gate and verified by IBM-Qiskit. An algorithmic design for an n:1 multiplexer is invented. In order to assess a PPM gate effectiveness, 13 standard Boolean functions and 8 standard types of gates are implemented. The PPM quantum gate is built using quantum assembly code (QAC), which runs on IBM Quantum Lab and IBM Quantum Composer platforms to measure the output qubits. Additional HA, muxes, and latches design led to the code creation in the Qiskit platform, which was used to measure the output qubits. A comparison of the D-latch, T-latch, JK-latch, and mux designs with existing circuits shows a reduction in quantum cost (qc) and junk output (go) and the implementation of a custom design in the IBM-Qiskit platform to measure output qubits is a first time in literature.

WITHDRAWN: Design of a novel 1-bit full adder with hybrid logic for full-swing, area-efficiency, and high-speed

In this paper, we propose a hybrid full-swing adder (HFSA) circuit that uses the hybrid full-swing logic (HFSL) technique, which consists of 20 transistors. This circuit relies heavily on a 12-transistor XOR-XNOR circuit to optimize the area and power. Our novel XOR-XNOR circuit plays a crucial role in achieving high-efficiency HFSA circuits. It integrates 2-to-1 multiplexers, pass transistor logic, and inverters to deliver glitch-free full-swing outputs. We compared the efficiency and practicality of our design with those of 10 alternatives by considering their performances and characteristics. Our novel XOR-XNOR circuit surpassed its counterparts with an exceptional chip area reduction of 14.14–28.01 %, an average power of 2.44 μW, and remarkably low delays of 25.88 and 24.87 ps. Notably, the proposed full adder achieved a chip area reduction of 11.30–49.69 %, 3.582 μW power, and a 72.66 ps delay. It emphasizes large-scale structures, such as 4-bit to 64-bit full adders, implemented using cascaded designs with a novel ripple carry adder. Using multipoint and Monte Carlo analysis in the ADEXL design suite to ensure the reliability of all circuits using the Cadence Virtuoso with the GPDK45 nm technology. The proposed method is an alternative to high-speed electronic systems with potential benefits.

Design and analysis of hybrid 10T adder for low power applications

Recently, a growing focus has been on the need for ultra-low-voltage (ULV) functioning to reduce energy usage. The full adder is a fundamental computational arithmetic unit in various image and signal processing applications. This study presents a novel architectural design for a 1-bit adder that utilizes 10 transistors. The concept relies on an energy-efficient hybrid logic multiplexer approach incorporating Gate Diffusion Input (GDI) logic. The primary goal of the suggested design for a hybrid full adder is to decrease power consumption while concurrently decreasing the required area. The suggested innovative architectural design for a full adder incorporates level restoration carry logic and ensures a complete swing output voltage. The designs have been analyzed in a standard environment using 45-nm CMOS process technology, with various supply voltages utilized. The evaluation of the adder cells focuses on speed, power consumption, power-delay-product (PDP), and space efficiency compared to the existing full adders. The recommended full adder cells were subjected to comprehensive simulation tests utilizing the Mentor Graphics environment. The results suggest that these cells surpass their counterparts, exhibiting a minimum of 80 % enhancements in their power-delay product (PDP) parameters. Also the comparisons have been made between the proposed full adders with and without level restoration techniques. The proposed level restoration technique based full adder yields better performance in terms of power and delay when compared to proposed full adder without level restoration.

Characterisation of graphene nano-ribbon field effect transistor and design of high performance PPN 12T GNRFET Full adder

Owing to the balanced electrical properties of graphene nanoribbon field effect transistors (GNRFETs), they are suitable next-generation devices for designing high performance circuits. However, as the fabrication for GNRFETs is at premature stage the performance of GNRFET device need to be explored with variation in its parameters. This article comprehensively analyses the impact of variations in GNRFET parameters on its threshold voltage, subthreshold swing and I ON /I OFF ratio. As an application example high performance PPN 12 T full adder is proposed using GNRFET device. The proposed full adder circuit shows dynamic power, propagation delay, low power-delay product and unity noise gain of 43.3 nW, 0.47 pS, 0.02 × 10−18 J and 0.46 respectively using supply voltage of 0.7 V. The performance of proposed full adder is compared with five previously proposed full adders using 16 nm GNRFET model in HSPICE simulation tool. Further, the impact of the GNRFET parameters on performance of proposed FA is investigated. A study of this nature is expected to improve performance of computing systems used in internet of things (IoT)-based infrastructure and health industry which demand for high performance next generation devices-based circuits.

Optimization and performance investigation of 1-Toffoli gate quantum full adders for spin-torque-based n-qubit architecture

Quantum computing (QC) is suitable for reversible computing due to its inherent parallel processing ability and fast speed. It also helps to address the issue of high-power dissipation in classical computing. Moreover, QC gates are the sequence of elementary operations such as single-qubit rotation and two-qubit entanglement. Elementary quantum operations are required to be reduced for the realization of complex computing. In this paper, optimization of 1-Toffoli gate-based quantum full adders (QFAs) in terms of the number of elementary operations with the help of quantum library {Ry, Rz, sqrt{mathrm{SWAP}}} is carried out. Moreover, the performance of two different 1-Toffoli QFAs is investigated in terms of execution time, fidelity, and number of electrons required to realize the QFAs. Improvement in fidelity is 0.7% and 0.57% for QFA1 and QFA2, respectively, compared to the fidelity of 2-Toffoli QFA. A 9.97% increase in execution time is mandatory for the QFA2 compared to QFA1. The QFA2 takes 5% more number of electrons in comparison to QFA1.

The Resistance Analysis Attack and Security Enhancement of the IMC LUT Based on the Complementary Resistive Switch Cells

The resistive random access memory (RRAM) based in-memory computing (IMC) is an emerging architecture to address the challenge of the “memory wall” problem. The complementary resistive switch (CRS) cell connects two bipolar RRAM elements anti-serially to reduce the sneak current in the crossbar array. The CRS array is a generic computing platform, for the arbitrary logic functions can be implemented in it. The IMC CRS LUT consumes fewer CRS cells than the static CRS LUT. The CRS array has built-in polymorphic characteristics because the correct logic function cannot be distinguished based on the circuit layout. However, the logic state of every CRS cell can be readout after each operation. It helps the attacker to recover the correct function of the IMC CRS LUT. This work discusses the resistance analysis attack of the IMC LUT based on the CRS array. The proposed resistance analysis attack method is able to be applied to different computation styles based on the CRS array, such as the CRS IMPLY, CRS NOR-OR/NAND-AND, and so on. The attacker can recover the logic function of the LUT by tracing the states of CRS cells. Furthermore, an improved IMC CRS LUT method is proposed and discussed to enhance security. The simulation and analysis results show that the improved IMC CRS LUT can resist various attacks, and it maintains the polymorphic characteristics of the IMC CRS LUT. And the N-bit full adder circuit based on the improved IMC CRS NOR-OR LUTs achieves the best performance compared with the previous counterparts.

Highly efficient low-area gate-diffusion-input-based approximate full adders for image processing computing

Highly efficient low-area gate-diffusion-input-based approximate full adders for image processing computing

Efficient co-planar adder designs in quantum dot cellular automata: Energy and cost optimization with crossover elimination

Quantum dot cellular automata (QCA) stands as a highly promising nanotechnology, capable of outperforming conventional CMOS technology. Leveraging its advantages, this paper addresses the challenges in adder circuits related to size, delay, and cost by integrating QCA technology. A novel layout for a co-planar full adder in QCA is introduced, featuring a half-adder design with 23 cells in a single layer without any crossover, achieving a delay of 0.25 clock cycles. By utilizing inter-cellular effects inherent in QCA technology, the presented designs offer significant improvements in a variety of design metrics, and a cost efficiency of 64.3%, distinguishing them from traditional logic design approaches. Additionally, in order to ensure an efficient routing channel and a consistent structure of the adder design, a Universal, Scalable, and Efficient (USE) clocking scheme has also been employed. The adder design is further used to build 4-bit and 8-bit Ripple Carry Adders. An extensive study on energy dissipation using QCADesigner-E and QCAPro tools is conducted for three tunneling energies (0.5 Ek, 1 Ek, and 1.5 Ek). The full adder design showcases substantial improvement in energy to delay cost when compared to the closest reported design, achieving improvements of 91.66%, 89.03%, and 88% at 0.5 Ek, 1 Ek, and 1.5 Ek, respectively. The results highlight enhanced circuit efficiency and streamlined layouts, outperforming existing models and offering substantial benefits to high-performance and energy-efficient computing systems.

1-bit full adder design using next generation semiconductor devices and performance benchmarking at low supply voltages

1-bit full adder design using next generation semiconductor devices and performance benchmarking at low supply voltages