Design and analysis of hybrid 10T adder for low power applications

Abstract

Recently, a growing focus has been on the need for ultra-low-voltage (ULV) functioning to reduce energy usage. The full adder is a fundamental computational arithmetic unit in various image and signal processing applications. This study presents a novel architectural design for a 1-bit adder that utilizes 10 transistors. The concept relies on an energy-efficient hybrid logic multiplexer approach incorporating Gate Diffusion Input (GDI) logic. The primary goal of the suggested design for a hybrid full adder is to decrease power consumption while concurrently decreasing the required area. The suggested innovative architectural design for a full adder incorporates level restoration carry logic and ensures a complete swing output voltage. The designs have been analyzed in a standard environment using 45-nm CMOS process technology, with various supply voltages utilized. The evaluation of the adder cells focuses on speed, power consumption, power-delay-product (PDP), and space efficiency compared to the existing full adders. The recommended full adder cells were subjected to comprehensive simulation tests utilizing the Mentor Graphics environment. The results suggest that these cells surpass their counterparts, exhibiting a minimum of 80 % enhancements in their power-delay product (PDP) parameters. Also the comparisons have been made between the proposed full adders with and without level restoration techniques. The proposed level restoration technique based full adder yields better performance in terms of power and delay when compared to proposed full adder without level restoration.