Full Adder Circuit Research Articles

Investigation of PNN Inverter-Based Low PDP 12T GNRFET Full Adder for VLSI Signal Processing Applications

When an adder circuit, which uses less power and operates at a higher speed, is introduced as a fundamental building block, the multiplier, arithmetic and logic unit (ALU), and digital system’s power delay product (PDP) performance can be easily improved. The graphene nanoribbon field effect transistor (GNRFET) used in very large-scale integrated (VLSI) circuits was developed in the submicron regime and offers superior electrical properties to the MOS transistor. This research paper introduces a full-adder circuit containing twelve GNRFETs (12T GF-FA). Calculations have been made about the introduced 12T GF-FA’s power usage, speed, PDP and leakage power. A few of the existing full adders with 8–32 transistors are compared to the performance of the newly proposed 12T GF-FA in terms of power and delay. For this comparison, some conventional full adders with 8–32 transistors have been implemented using 16[Formula: see text]nm technology GNRFETs. The pull-down network of the suggested adder has two stacked GNRFETs. The proposed adder’s current conduction and power consumption are reduced by the use of stacked transistors. According to the simulation results, the PDP of the suggested 12T GF-FA is 73.2–99% lower when compared to other full adders considered state-of-the-art. Additionally, it has been researched and documented how variations in the PVT and GNRFET parameters affect the performance of full-adder circuits. The proposed adder, with its low PDP, is especially suitable for VLSI signal processing applications. The simulation was carried out using the HSPICE simulation tool and the 16[Formula: see text]nm MOS-GNRFET model.

Ln3+-doped glasses: Advancing molecular logic for integration into photonic and electronic devices

The rapid miniaturization of electronic devices has pushed the limits of conventional silicon-based technologies, creating a pressing need for novel approaches to sustain the exponential growth of computing power. This study explores the innovative application of Ln3+-doped glasses in developing molecular logic systems as a potential solution. Exploiting Eu3+ and Dy3+, we investigated the luminescence properties under various physical stimuli such as excitation wavelength and temperature. Our findings reveal the capability to construct logic elements of varying complexity, from simple AND and OR gates to advanced FULL-ADDER and FULL-SUBTRACTOR circuits. This work represents the first instance of using Ln3+ exclusively for molecular logic via physical stimuli. The robust and stable optical properties of the doped glasses enable their integration into conventional electronic and photonic devices, potentially revolutionizing the landscape of molecular logic and computing. This research not only enhances the understanding of light-matter interactions in Ln3+-doped systems but also opens new pathways for the development of miniaturized, high-performance innovative computational devices.

Review of Carbon Nanotube Field Effect Transistor for Nanoscale Regime

Background: The need for high performance, small size, low delay, low power consumption, and long battery backup of portable systems is increasing with the advancement of technology. Many features of portable systems can be improved using scaling methods. In the scaling process, reducing the size of devices causes serious difficulties, including the short channel effect (SCE) and leakage current, which degenerates the characteristics of the systems. Objective: In this review paper, a trending carbon nanotube field effect transistor (CNTFET) technology is discussed in detail. CNTFET can replace the conventional metal oxide semiconductor field effect transistor (MOSFET) technology to overcome the SCE problems in the nanoscale regime and also meet the requirements of portable systems. Methods: The CNTFET is an extremely good nanoscale technology due to its one-dimension band structure, high transconductance, high electron mobility, superior control over channel formation, and better threshold voltage. This technology is used to construct high-performance and low-power circuits by replacing the MOSFET technology. CNTFET in comparison to MOSFET takes the carbon nanotube (CNT) as a channel region. Results: The value of threshold voltage in CNTFET changes with the diameter of CNT. The threshold voltage of the devices controls many parameters at the circuit-level design. Hence, the detailed operation and the characteristics of CNTFET devices are presented in this review paper. The existing CNTFET-based ternary full adder (TFA) circuits are also described in this review paper for the performance evaluation of different parameters. Conclusion: CNTFET technology is the possible solution for the SCE in the nanoscale regime and is capable to design efficient logic circuits. The circuits using the CNTFET technology can provide better performance and various advantages, including fast speed, small area, and low power consumption, in comparison to the MOSFET circuits. Thus, CNTFET technology is the best choice for circuit designs at the nanoscale.

Comparative Analysis of High Speed and Area Efficient Full-Adder using CMOS and MGDI Techniques

Extremely quick processing is crucial for very large-scale integrated (VLSI) circuits in the arithmetic logic unit. Complementary metal oxide semiconductor (CMOS) and modified gate diffusion input (MGDI) are beneficial technologies for designing high-speed circuits with better reliability and performance with regard to area and power consumption. This research work provides a comparative performance analysis of a full adder that is implemented with CMOS and MGDI technology. This work aims to develop a CMOS-based full-adder and a MGDI-based full-adder circuit for area-efficient and high-speed applications. First, the analysis and implementation of the XOR and NAND logic gates are designed using CMOS technology and the MGDI technique to create a full-adder design. The comparative analysis of integrated circuits in CMOS and MGDI technologies is primarily determined by the number of transistors and delay time. The full-adder is designed and analyzed using 90 nm technology, with performance characteristics evaluated using Cadence Virtuoso Tools.

Impact of Variability on Novel Transistor Configurations in Adder Circuits at 7nm FinFET Technology

This research work focuses on implementation of the FinFET-based complementary metal-oxide-semiconductor (CMOS) Full Adder circuits for different transistor configurations using ASAP7 FinFET model. First, this work examines FinFET-based AND-OR-invert (AOI) gates using different topologies, and second, a FinFET-based CMOS Full Adder circuit at the 7[Formula: see text]nm technology node is analyzed with respect to its process, voltage and temperature (PVT) variability effect measured in terms of the normalized standard deviation of different performance metrics. The comparison is made between conventional (CFFA1) and proposed (FFA2, FFA3, FFA4, FFA5, FFA6, FFA7 and FFA8) FinFET-based CMOS full adder circuits. The aim is to determine the optimal design configuration of the FinFET full adder circuit with the minimum impact of PVT variability. On examining the power delay product (PDP) variability, it is found that variations in FFA2, FFA3, FFA4, FFA5, FFA6, FFA7 and FFA8 are significantly lower than CFFA1 by 6.30%, 4.68%, 10.30%, 65.48%, 68.05%, 65.61% and 17.20%, respectively. Among all the proposed configurations, normalized standard deviation [Formula: see text] for the PDP metric is lowest in FFA6, followed by FFA7, FFA5, FFA8, FFA4, FFA2 and FFA3. The normalized standard deviation [Formula: see text] for power dissipation, however, is lowest in FFA8. In addition, a layout comparison analysis of conventional and proposed full adder circuits reveals that FFA7 has the least area, followed by FFA8, FFA6, FFA5, FFA3, FFA4, FFA2 and CFFA1. The area of FFA2, FFA3, FFA4, FFA5 and FFA6 has decreased by 3.29%, 3.51%, 3.50%, 5.14% and 5.52%, while FFA7 and FFA8 have experienced a decrease in area by 13.87% and 14.36%, respectively, as compared to conventional CFFA1. The proposed layout of FinFET-based CMOS Full Adders can be directly transferred into the foundry’s production line for manufacturing purposes. The overall investigation led us to conclude that FFA8 is the most efficient of all due to the lowest power variation, lower delay variation and lower PDP variation, moreover it has a reduced layout area among all the discussed designs. However, there is a tradeoff in terms of penalty in nominal power, propagation delay and PDP in the proposed topologies.

Programmable Threshold Logic Implementations in a Memristor Crossbar Array.

In this study, we demonstrate the implementation of programmable threshold logics using a 32 × 32 memristor crossbar array. Thanks to forming-free characteristics obtained by the annealing process, its accurate programming characteristics are presented by a 256-level grayscale image. By simultaneous subtraction between weighted sum and threshold values with a differential pair in an opposite way, 3-input and 4-input Boolean logics are implemented in the crossbar without additional reference bias. Also, we verify a full-adder circuit and analyze its fidelity, depending on the device programming accuracy. Lastly, we successfully implement a 4-bit ripple carry adder in the crossbar and achieve reliable operations by read-based logic operations. Compared to stateful logic driven by device switching, a 4-bit ripple carry adder on a memristor crossbar array can perform more reliably in fewer steps thanks to its read-based parallel logic operation.

Full Adder Circuit Design with CMOS Technology Implementing with Artificial Neural Network with Verilog HDL Code for Output

The goal of this research is to create Full-Adder gate using a Complementary Metal Oxide Semiconductor (CMOS) and an Artificial Neural Network.We constantly bear in mind that any COMS circuit we design should be as inexpensive as possible.Multilayer ANN was employed in this work to create the circuit. Weights are employed to modify the value in our study, treating neurons as transistors and treating negative values as inverters.We are also designing Verilog-HdL Code to simply apply the full adder for experimenting an artificial neural network assigning weights to get appropriate results. Keywords: Full Adder, CMOS,ANN,Verilog-HDL

CMOS full adder cells based on modified full swing restored complementary pass transistor logic for energy efficient high speed arithmetic applications

In modern Digital System design, adders are widely used in many applications including Microprocessors, Digital Signal Processors, Arithmetic Logic Units and digital signal processing. Power efficiency is an important key factor for any integrated circuits. By considering the importance of Full Adder (FA) cells, their power consumption may play significant role in overall power consumption. So designing a low-power full adder is important to achieve the high-performance computing. Swing restored technique is commonly used method to reduce the signal swing at the internal nodes and it helps to reduce the power consumption and improves the circuit's speed. This paper presents a novel hybrid full adder cell design using the modified swing restored technique and complementary pass transistor logic. The Full Adder circuit was implemented using Cadence Virtuoso tool on gptk 180nm CMOS process technology. The proposed full adder was compared with earlier reported circuits based on Delay, Power and PDP. The comparison shows that proposed circuit consumes less power with high performance. Also various process corners and noise immunity were analyzed to find the sensitivity of the circuit. Further an 8-bit Ripple Carry Adder was designed using the proposed full adder to verify the functionality in higher order bits. Simulations were performed and analysed using the Cadence Spectre.

Design and Implementation of CMOS and Transmission Gate Based Full Adder Using 45nm Technology

Abstract: In electronic industry the level of integration is an important aspect as it makes the electronic device simpler and more reliable. The device density increases with the better level of integration. Power dissipation, Area occupied, and Propagation delay are some of the important factors that need to be considered. These parameters play a vital role in manufacturing portable electronic gadgets. Many binary adders are formed using full adders. Hence, if any enhancements have to be made to improve the performance, it can be made at the root level i.e., adders circuits itself. This in turn helps in bettering the performance of the electronics circuits which follow adder circuits. The low power VLSI design is of great importance due to portable electronic products. Full adder is a type of adder circuit that adds three inputs and gives two outputs. Out of three, two will be the present inputs and the third input will be the carry from the previous stage. ‘A’ and ‘B’ are the actual inputs, ‘C’ is the carry from the previous operation. SUM and CARRY OUT are the two outputs. In this work, Design and Implementation of full adder using conventional CMOS design and Transmission gate based Full adder circuits are carried out. At last comparison is made between the two designs with respect to power dissipation, delay and area (number of transistors). Cadence Virtuoso Tool is used in design and simulation conventional CMOS design and Transmission gate based Full adder circuits. The entire circuit is simulated in Cadence Tools at 45nm CMOS process.

Implementation and Analysis of CMOS and Pass Transistor Logic Based Full Adder Circuits

Abstract: In electronic industry the level of integration is an important aspect as it makes the electronic device simpler and more reliable. The device density increases with the better level of integration. Power dissipation, Area occupied and Propagation delay are some of the important factors that need to be considered. These parameters play a vital role in manufacturing portable electronic gadgets. Many binary adders are formed using full adders. Hence, if any enhancements have to be made to improve the performance, it can be made at the root level i.e., adders circuits itself. This in turn helps in bettering the performance of the electronics circuits which follow adder circuits. The low power VLSI design is of great importance due to portable electronic products. Full adder is a type of adder circuit that adds three inputs and gives two outputs. Out of three, two will be the present inputs and the third input will be the carry from the previous stage. ‘A’ and ‘B’ are the actual inputs, ‘C’ is the carry from the previous operation. SUM and CARRY OUT are the two outputs. In this work, Design and Implementation of full adder using conventional CMOS design and Pass Transistor Logic based Full adder circuits are carried out. At last comparison is made between the two designs with respect to power dissipation, delay and area (number of transistors). Cadence Virtuoso Tool is used in design and simulation conventional CMOS design and Pass Transistor Logic based Full adder circuits. The entire work is simulated in 180nm CMOS technology.

Design and implementation of high-performance 20-T hybrid full adder circuit

Design and implementation of high-performance 20-T hybrid full adder circuit

Power Efficient Implementation of ECC Using LCSLA Based Dual Field Vedic Multiplier

The Elliptic Curve Cryptographic (ECC) technique is employed for security standards such as Security Key Management (SKM), digital signature, data authentication and so on. The ECC technique is capable of sequential and parallel mode processes through a unified design. It is used for both equally binary fields and prime fields of cryptosystems. The DMM structure has been developed using CSA. This adder requires a greater amount of Full Adder circuits, which occupy more area. To overcome this problem, this paper discusses four different methods, such as DMM-Optimized Carry Look Ahead Adder, DMM-Optimized Carry Bypass Adder, DMM-Look up Table Carry Select Adder, and Dual Field Vedic Multiplier – LCSLA, which is used to increase the performance of the ECC. The parameters like power utilization, time delay information, and hardware area overhead are analyzed and compared with existing methods. Among those four methods, the DVM-LCSLA method gave better results in FPGA and ASIC performances.

Characterisation of graphene nano-ribbon field effect transistor and design of high performance PPN 12T GNRFET Full adder

Owing to the balanced electrical properties of graphene nanoribbon field effect transistors (GNRFETs), they are suitable next-generation devices for designing high performance circuits. However, as the fabrication for GNRFETs is at premature stage the performance of GNRFET device need to be explored with variation in its parameters. This article comprehensively analyses the impact of variations in GNRFET parameters on its threshold voltage, subthreshold swing and I ON /I OFF ratio. As an application example high performance PPN 12 T full adder is proposed using GNRFET device. The proposed full adder circuit shows dynamic power, propagation delay, low power-delay product and unity noise gain of 43.3 nW, 0.47 pS, 0.02 × 10−18 J and 0.46 respectively using supply voltage of 0.7 V. The performance of proposed full adder is compared with five previously proposed full adders using 16 nm GNRFET model in HSPICE simulation tool. Further, the impact of the GNRFET parameters on performance of proposed FA is investigated. A study of this nature is expected to improve performance of computing systems used in internet of things (IoT)-based infrastructure and health industry which demand for high performance next generation devices-based circuits.

The Resistance Analysis Attack and Security Enhancement of the IMC LUT Based on the Complementary Resistive Switch Cells

The resistive random access memory (RRAM) based in-memory computing (IMC) is an emerging architecture to address the challenge of the “memory wall” problem. The complementary resistive switch (CRS) cell connects two bipolar RRAM elements anti-serially to reduce the sneak current in the crossbar array. The CRS array is a generic computing platform, for the arbitrary logic functions can be implemented in it. The IMC CRS LUT consumes fewer CRS cells than the static CRS LUT. The CRS array has built-in polymorphic characteristics because the correct logic function cannot be distinguished based on the circuit layout. However, the logic state of every CRS cell can be readout after each operation. It helps the attacker to recover the correct function of the IMC CRS LUT. This work discusses the resistance analysis attack of the IMC LUT based on the CRS array. The proposed resistance analysis attack method is able to be applied to different computation styles based on the CRS array, such as the CRS IMPLY, CRS NOR-OR/NAND-AND, and so on. The attacker can recover the logic function of the LUT by tracing the states of CRS cells. Furthermore, an improved IMC CRS LUT method is proposed and discussed to enhance security. The simulation and analysis results show that the improved IMC CRS LUT can resist various attacks, and it maintains the polymorphic characteristics of the IMC CRS LUT. And the N-bit full adder circuit based on the improved IMC CRS NOR-OR LUTs achieves the best performance compared with the previous counterparts.

Ternary arithmetic and logic unit with carbon nanotube-based field-effect transistors for ultra-low power and high-speed applications

<span>The number of consumers for different applications has expanded tremendously as a result of the growth of consumer electronics-related applications in numerous sectors. Customers often need high-speed applications that use a minimal amount of power for a variety of applications like signal processing, picture processing, communication systems, and so on. The speed of a ternary logic-based design might be greater than that of a binary logic-based one. In this study, a novel architecture for arithmetic and logic units (ALUs) is proposed. The design makes use of ternary logic. In order to accomplish both low power consumption and high performance, methodologies for designing carbon nanotube-based field-effect transistors (CNTFETs) are employed. The method that has been suggested is able to carry out operations such as addition, subtraction, multiplication, reasoning, and comparison. After developing the recommended model, it is compared to earlier designs for power delay product (PDP), average power consumption, and maximum delay duration. The simulation findings show that the carbon nanotube field effect transistors (CNTFET) based ternary ALU circuits outperformed conventional ternary full adder circuits. The suggested design had a delay time of 13.94 ps and a PDP of 5.32 aJ, while the old design had a delay time of 17.67 ps and a PDP of 51.38 aJ.</span>

Enhanced Quasi-Static Energy Recovery and Modified Clock Gating for the Wallace Tree Multiplier with Reversible Adders

High-speed, low-power digital circuits are essential in many digital applications. The objective of the paper is to design high-speed low-power multipliers with reversible gates. The realization of a multiplier with an efficient clocking system is also presented to reduce leakage power consumption. The existing reversible configurations do not possess an effective clocking system for reducing power in an idle state. In this work, a modified clock gating (MCG) and Enhanced Quasi-Static Energy Recovery Logic (EQSERL) are designed to generate a clock pulse. The EQSERL reduces the dynamic state in the circuit and it is designed with reduced complexity. This process effectively reduces leakage power consumption in the circuit. The conventional clock gating circuit is modified for connecting it with the EQSERL. This MCG circuit reduces unwanted power consumption. The conventional Wallace tree multiplier (WTM) involves full adder and half adder circuits. In this proposed work, a square root carry select adder (SQRT CSLA) with a reversible binary to excess-1 converter (BEC) and a ripple carry adder is presented. The reversible gates such as the Feynman gate, the Toffoli gate, and the dual key gate are employed. Finally, the proposed architecture is tested with different clocking circuits using Synopsys tools and the performance metrics like delay and power are observed.

Investigation on floating-gate field-effect transistor for logic-in-memory application

In this paper, we present analysis results on the applicability of a previously introduced memory device, floating-gate field-effect transistor (FGFET), to a logic-in-memory (LiM) system for the first time. Device optimization and compact modeling were performed using a well-calibrated technology computer-aided design model and the results of applying LiM circuits were arranged. Device optimization in the 32 nm technology node was conducted by assessing the device performance in terms of memory window, retention time, and write speed. After device optimization, the operational characteristics were analyzed by applying the proposed compact model to a full adder (FA) circuit and a ternary content addressable memory (TCAM) circuit with LiM characteristics. Compared to FA and TCAM circuits composed of conventional FETs, the FGFET-based circuits demonstrated superior performance in terms of area and operating characteristics, implying that they offer significant potential for applications in silicon-based LiM technology.

Energy Efficient Compressor Cell for Low Power Computing

As the use of multimedia devices is rising, power management is becoming a major challenge. Various types of compressors have been designed in this study. Compressor circuits are designed using several circuits of XOR-XNOR gates and multiplexers. XOR-XNOR gate combinations and multiplexer circuits have been used to construct the suggested compressor design. The performance of the proposed compressor circuits using these low-power XOR-XNOR gates and multiplexer blocks has been found to be economical in terms of space and power. This study proposes low-power and high-speed 3-2, 4-2, and 5-2 compressors for digital signal processing applications. A new compressor has also been proposed that is faster and uses less energy than the traditional compressor. The full adder circuit, constructed using various combinations of XOR-XNOR gates, has been used to develop the proposed compressor. The proposed 3-2 compressor shows average power dissipation 571.7 nW and average delay 2.41 nS, 4-2 compressor shows average power dissipation 1235 nW and average delay 2.7 nS while 5-2 compressor shows average power dissipation 2973.50 nW and average delay 3.75 nS.

Low-Power Pass-Transistor Logic-Based Full Adder and 8-Bit Multiplier

With the rapid development of information technology, the demand for high-speed and low-power technology for digital signal processing is increasing. Full adders and multipliers are the basic components of signal processing technology. Pass-transistor logic is a promising method for implementing full adder and multiplier circuits due to the low count of transistors and low-power characteristics. In this paper, we present a novel full adder based on pass transistors. The proposed full adder consists of 18 transistors. The post-layout simulation shows a 13.78% of power reduction compared to conventional CMOS full adders. Moreover, we propose an 8-bit signed multiplier based on the proposed full adder. The post-layout simulation shows an 8% power reduction compared to the multiplier produced by the Design Compiler synthesis tool. Compared to the existing work with a similar process, our work achieved only 19.02% of the power-delay product and 3.5% of the area-power product.

Assessment of a universal logic gate and a full adder circuit based on CMOS-memristor technology

The study of memristor-based digital logic circuits is a new approach in non-conventional computation frameworks because of the memristor's properties, especially the ability to store data and perform logic operations. Using memristors, in this work, we have analyzed in terms of variability basic AND/OR Universal Logic Gates (ULG) and a Full adder implementation at the circuit-level in LT-spice. We first implement and calibrate a memristor's model with data obtained from IV curves of HfO2-based ReRAM to do it. The data demonstrate that although buffers are used to restore the signal, memristors variability affects the output voltage and the circuit's performance.