Front-end Circuit Research Articles

A LoRaWAN Carbon Monoxide Measurement System With Low-Power Sensor Triggering for the Monitoring of Domestic and Industrial Boilers

Gases emitted by domestic and industrial boilers significantly contribute to the overall pollution levels of urban environments. Among these gases, carbon monoxide (CO) represents a marker of the efficiency of the combustion processes, and the monitoring of its emissions, even if often neglected, is crucial to improve energy efficiency and environmental safety within a smart city context. This article aims at describing a real-time, remote system for the monitoring of CO emissions of domestic and industrial boilers based on the use of a low-power long-range wide-area network (LoRaWAN) sensor node. In particular, the proposed solution is based on an ad hoc front-end circuit acting as a power-gating system for the rest of the sensor node, exploiting the output of the CO sensor as a trigger to activate the data acquisition and transmission module. Such a solution allows to notably increase the lifetime of the node, allowing its powering using rechargeable Li-ion batteries. Tests were performed on a real boiler in order to demonstrate the validity of the proposed solution. Power consumption of the sensor node was experimentally measured: theoretical analysis demonstrated an ideal lifetime for the sensor node up to two and half years.

An Integrated Front-end Circuit Board for Air-Coupled CMUT Burst-Echo Imaging

To conduct burst-echo imaging with air-coupled capacitive micromachined ultrasonic transducers (CMUTs) using the same elements in transmission and reception, this work proposes a dedicated and integrated front-end circuit board design to build an imaging system. To the best of the authors’ knowledge, this is the first air-coupled CMUT burst-echo imaging using the same elements in transmission and reception. The reported front-end circuit board, controlled by field programmable gate array (FPGA), consisted of four parts: an on-board pulser, a bias-tee, a T/R switch and an amplifier. Working with our 217 kHz 16-element air-coupled CMUT array under 100 V DC bias, the front-end circuit board and imaging system could achieve 22.94 dB signal-to-noise ratio (SNR) in burst-echo imaging in air, which could represent the surface morphology and the three-dimensional form factor of the target. In addition, the burst-echo imaging range of our air-coupled CMUT imaging system, which could work between 52 and 273 mm, was discussed. This work suggests good potential for ultrasound imaging and gesture recognition applications.

A 4-bit 36 GS/s ADC with 18 GHz Analog Bandwidth in 40 nm CMOS Process

This paper presents a 4-bit 36 GS/s analog-to-digital converter (ADC) employing eight time-interleaved (TI) flash sub-ADCs in 40 nm complementary metal-oxide-semiconductor (CMOS) process. A wideband front-end matching circuit based on a peaking inductor is designed to increase the analog input bandwidth to 18 GHz. A novel offset calibration that can achieve quick detection and accurate correction without affecting the speed of the comparator is proposed, guaranteeing the high-speed operation of the ADC. A clock distribution circuit based on CMOS and current mode logic (CML) is implemented in the proposed ADC, which not only maintains the speed and quality of the high-speed clock, but also reduces the overall power consumption. A timing mismatch calibration is integrated into the chip to achieve fast timing mismatch detection of the input signal which is bandlimited to the Nyquist frequency for the complete ADC system. The experimental results show that the differential nonlinearity (DNL) and integral nonlinearity (INL) are −0.28/+0.22 least significant bit (LSB) and −0.19/+0.16 LSB, respectively. The signal-to-noise-and-distortion ratio (SNDR) is above 22.5 dB and the spurious free dynamic range (SFDR) is better than 35 dB at 1.2 GHz. An SFDR above 24.5 dB and an SNDR above 18.6 dB across the entire Nyquist frequency can be achieved. With a die size of 2.96 mm * 1.8 mm, the ADC consumes 780 mW from the 0.9/1.2/1.8 V power supply.

Peak tailing cancellation techniques for digital CR-(RC)n filter

The CR-(RC)n filter is used for Semi-Gaussian pulse shaping in analog spectroscopy. A new digital CR-(RC)n filter is presented based on the recursive models of the CR filter and RC filter. The spectroscopic signal reconstruction technique is proposed. This technique is applied to digital exponential decay signals obtained by the digitization of analog signals that represent the combined response of a FAST-SDD detector and the associated front-end circuit. Compared with the direct application of the digital CR-(RC)n filter, the technique eliminates the undershoot of the Semi-Gaussian pulse which is the primary cause of the low-energy peak tailing. And, the digital pole-zero cancellation filter follows digital CR-(RC)n filter to reduce the long tail of the shaped Semi-Gaussian pulse which leads to the high-energy peak tailing. Experimental results based on XRF signals of manganese sample show that the proposed techniques can cancel peak tailing due to the shaped Semi-Gaussian pulse improving FWTM/FWHM ratio and throughput capability.

Millimeter-Wave Broadband Substrate Integrated Magneto-Electric Dipole Arrays With Corporate Low-Profile Microstrip Feeding Structures

A millimeter-wave (mm-Wave) broadband linearly polarized (LP) substrate integrated magneto-electric dipole (ME-dipole) with a low-profile microstrip feeding structure covering the 22–33 GHz band is proposed in this article. It owns a good performance, particularly in terms of bandwidth and gain flatness. Importantly, the proposed substrate integrated LP ME-dipole element can be easily expanded into a full-corporate fed array without bandwidth degradation and requiring additional dielectric substrates. Moreover, its low-profile microstrip feeding structure locating on a hybrid substrate (include a thin dielectric substrate and a bonding film) makes the antennas amenable for direct integration with mm-Wave front-end circuits. Design, fabrication, and measurement of two arrays containing $4 \times 4$ and $8\,\, \times \,\, 8$ ME-dipoles are carried out, respectively. The measured results agree well with the simulated ones, validating the correctness of the proposed designs. The measured results of the $4 \times 4$ and $8\times 8$ array antennas show that both the two prototypes exhibit a wide available bandwidth (considering |S11| < −10 dB and 3 dB gain bandwidth) of more than 44%, a cross-polarization level of lower than −35 dB, a low-profile feeding layer of only 0.227 mm, a peak gain of 19.18 and 25 dBi, respectively, etc. The exhibited performance metrics of the proposed array antennas are promising for a number of applications ranging from 5G communications, satellite communications, to automotive radars, and so on.

In brief

PAGE 1103 Researchers from the Republic of Korea present a self-capacitance sensing technique for touch screen panels with alternating panel charge sharing, which effectively suppresses low-frequency noise and achieves better signal-to-noise ratio. SNR is improved by 7.65 dB compared to conventional panel charge sharing based techniques. PAGE 1148 A deep reinforcement learning-based approach for the delay-constrained buffer-aided relay selection in a cooperative cognitive network is proposed by Chinese researchers. The proposed algorithm can solve the complicated relay selection problem and achieves the optimal throughput when the buffer size and number of relays is large. Schematic of proposed analog front-end circuit. PAGE 1111 Brazilian researchers present an alternative analysis method to derive the voltage-current transmission matrix of transmission line sections. The method efficiently computes the relationship between the voltages and currents at the input and output of a circuit modelled through N identical cascaded two-port networks. The overall framework of the proposed Q-Learning algorithm. PAGE 1116 Researchers from Daejeon, Republic of Korea, present a new method for training convolutional neural networks that are designed to detect targets of interest in hyperspectral images. Using synthetic training data only, a Siamese CNN has been trained to learn robust features for the detection task. Experimental results on real hyperspectral images show the effectiveness of the proposed method. Circuit model composed of N identical cascaded two-ports. PAGE 1130 Indian researchers have designed and presented a photonic configurable logic block with a 1×1 Mach-Zehnder modulator as a universal photonic gate, capable of performing logical operations with the help of a field-programmable gate array as a configuration controller. The device exhibits neglibile transmission loss and a flexible switching control when compared to existing 2×2 MZI-basd photonic gates. A band image from the hyperspectral data cube (l) and ground truth for targets of interest (r). Cross-section details of the designed 1×1 Mach-Zehnder modulator.

A Low Walk Error Analog Front-End Circuit With Intensity Compensation for Direct ToF LiDAR

An analog front-end (AFE) circuit comprising an amplifier module, a peak detector, and a timing discriminator has been designed to facilitate the target identification for direct time-of-flight (dToF) LiDAR. The amplitude saturation error (ASE) is compensated in this article for the intensity determination, which is conducted based on the combination of the pulse width and peak detector. Together with the improved walk error compensation scheme, the proposed AFE circuit can attain the distance and intensity information simultaneously with lower cost and larger dynamic range. A specific frequency compensation method is proposed with a shunt feedback TIA, which improves the stability and mitigates the impact of the package parasitics. The measured -3-dB bandwidth, transimpedance gain, and the input-referred noise current are 281 MHz, 86 dB <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula> , and 4.68 pA/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\surd $ </tex-math></inline-formula> Hz respectively. The proposed AFE circuit, which is fabricated in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.18~\mu \text{m}$ </tex-math></inline-formula> CMOS technology, achieves the distance accuracy of ±30 ps and the intensity accuracy of ±4% in the dynamic range of 1:5000 without gain control scheme.

Design of Low-Power Low-noise CMOS ECG Amplifier for Smart Wearable Device

The artificial intelligence health care devices have focused on the portability and accuracy and the most trending area of wearable biomedical application has become the electrocardiogram (ECG) recording device. The ECG signals have the characteristic of low amplitude, prone to be influenced by Power Line Interference (PLI), so it is essential to achieve high gain and high common-mode rejection ratio (CMRR),while the input-referred noise and power consumption need to be low to realize the cardiac screening system on chip (Soc).In this paper, a low-noise low-power analog front end (AFE) amplifier which based on Driven-Right-Leg circuit(DRL) has been proposed. It was implemented in CMOS 180 nm with bias current and supply voltage of 12µA and 0.7V, respectively. The simulation results showed that this front-end circuit can achieve a low input referred noise of 4.11µV/Hz and high common mode rejection ratio of 135dB. It also gave voltage gain of 41.8 dB with the bandwidth from 0.1Hz to 100Hz and the total power consumption was 4.32µW. Compared with recently relevant whole circuit design, we believe that it is suitable to be used in smart wearable device.

Synchronization and Calibration of the 24-Modules J-PET Prototype With 300-mm Axial Field of View

Research conducted in the framework of the J-PET project aims to develop a cost-effective total-body positron emission tomography scanner. As a first step on the way to construct a full-scale J-PET tomograph from long strips of plastic scintillators, a 24-strip prototype was built and tested. The prototype consists of detection modules arranged axially forming a cylindrical diagnostic chamber with the inner diameter of 360 mm and the axial field-of-view of 300 mm. Promising perspectives for a low-cost construction of a total-body PET scanner are opened due to an axial arrangement of strips of plastic scintillators, wchich have a small light attenuation, superior timing properties, and the possibility of cost-effective increase of the axial field-of-view. The presented prototype comprises dedicated solely digital front-end electronic circuits and a triggerless data acquisition system which required development of new calibration methods including time, thresholds and gain synchronization. The system and elaborated calibration methods including first results of the 24-module J-PET prototype are presented and discussed. The achieved coincidence resolving time equals to CRT = 490 $\pm$ 9 ps. This value can be translated to the position reconstruction accuracy $\sigma(\Delta l) =$ 18 mm which is fairly position-independent.

A 10-bit SAR ADC using novel LSB-first successive approximation for reduced bitcycles

This paper presents a 10-bit ultra-low power least-significant bit first (LSB-first) successive approximation register analog-to-digital converter used in wearable electrocardiogram monitoring. Compared with the exsiting ones, the number of bitcycles taken in the proposed LSB-first scheme only relates to the difference between two adjacent samples and the capacitor array is reduced by 50%. Fabricated in 65 ​nm CMOS technology within a bio-sensor front-end circuit, the proposed LSB-first SAR ADC occupies an active area of 200 ​× ​450 ​μm2, consumes 60.8 ​nW ​at 10 ​kHz sampling rate, and achieves 58.4 ​dB SNDR.

Preliminary Evaluation of a Wearable Sensor System for Heart Rate Assessment in Guide Dog Puppies

This paper details the development of a novel wireless heart rate sensing system for puppies in training as guide dogs. The system includes a harness with on-board electrocardiography (ECG) front-end circuit, inertial measurement unit and a micro-computer with wireless capability where the major research focus of this paper was on the ergonomic design and evaluation of the system on puppies. The first phase of our evaluation was performed on a Labrador Retriever between 12 to 26 weeks in age as a pilot study. The longitudinal weekly data collected revealed the expected trend of a decreasing average heart rate and increased heart rate variability as the age increased. In the second phase, we improved the system ergonomics for a larger scale deployment in a guide dog school (Guiding Eyes for the Blind (Guiding Eyes)) on seventy 7.5-week-old puppies (heart rate coverage average of 86.7%). The acquired ECG based heart rate data was used to predict the performance of puppies in Guiding Eyes’s temperament test. We used the data as an input to a machine learning model which predicted two Behavior Checklist (BCL) scores as determined by expert Guiding Eyes puppy evaluators with an accuracy above 90%.

Digital Electronics as RFID Tags: Impedance Estimation and Propagation Characterization at 26.5 GHz and 300 GHz

This article presents a circuit impedance model and results of propagation characterization at 26.5 GHz and 300 GHz for a new type of RFID tag that is based on digital electronics. This RFID tag leverages the backscatter radio generated from switching of transistors inside digital circuits, which does not need antennas or RF front-end circuits thereby further reducing the device’s form factor. Moreover, the proposed RFID tag is compatible with a wide range of interrogating frequencies and can be implemented on existing electronics without additional cost. The proposed circuit impedance model explains the modulation mechanism of this new backscatter radio and provides an estimation of digital circuits’ impedance using SPICE model parameters. Based on the proposed circuit impedance model, we develop a modified modulation loss factor to estimate the modulation loss resulting from the switching activity of the digital electronics. Furthermore, propagation characterization is conducted at 26.5 GHz and 300 GHz, where the shadowing gain for the carrier power and the backscattered power is characterized as 3.93 dB and 0.96 dB at 26.5 GHz, and 1.01 dB and 0.52 dB at 300 GHz, respectively, showing that the backscatter channel can provide a more reliable link that is resistant to the constructive and destructive interference from the multipaths as compared to the carrier channel.

Analytical Study of Front-End Circuits Coupled to Silicon Photomultipliers for Timing Performance Estimation under the Influence of Parasitic Components.

Full exploitation of the intrinsic fast timing capabilities of analog silicon photomultipliers (SiPMs) requires suitable front-end electronics. Even a parasitic inductance of a few nH, associated to the interconnections between the SiPM and the preamplifier, can significantly degrade the steepness of the detector response, thus compromising the timing accuracy. In this work, we propose a simple analytic expression for the single-photon response of a SiPM coupled to the front-end electronics, as a function of the main parameters of the detector and the preamplifier, taking into account the parasitic inductance. The model is useful to evaluate the influence of each parameter of the system on the slope of its response and to guide the designer in the definition of the architecture and the specifications for the front-end electronics. The results provided by the model have been successfully compared with experimental measurements from a front-end circuit with variable configuration based on a bipolar junction transistor (BJT), coupled to a 3 × 3 mm2 SiPM stimulated by a fast-pulsed laser source.

Low-Cost Millimeter-Wave Circularly Polarized Planar Integrated Magneto-Electric Dipole and Its Arrays With Low-Profile Feeding Structures

A low-cost millimeter-wave circularly polarized (CP) planar integrated magneto-electric dipole (ME-dipole) element with simple structure is proposed, which is fed by a low-profile feeding structure capable of being directly integrated with Ka -band front-end circuits. Two rotationally symmetrical L-shaped patches are adopted to replace the two straight arms of the original linearly polarized ME-dipole to generate a rotated electric field, thus radiating CP waves. Based on this CP ME-dipole element, CP array antennas containing 2 × 2 and 4 × 4 radiators with low-profile full-corporate feeding networks are developed without any additional dielectric layer. Prototypes of these two CP array antennas are fabricated and measured. Good agreement between the simulated and measured results is achieved, validating the correctness of these two designs. The 2 × 2 array exhibits a | S 11| Ka -band satellite communications, etc.

Actively Simulated Floating Lossless Inductor for Short Range Wireless Communication

This communication describes the resistorless simulation of the floating lossless inductor using three voltage differencing buffered amplifiers (VDBAs) and one grounded capacitor. The circuit employs only a grounded capacitor, and no other extra resistor element is employed. Thus, it is suitable for further communication integrated front-end circuit design in short-range wireless and application. The realized equivalent inductance value of the simulated inductor can be changed electronically via the external biasing currents of the VDBAs. Sufficient simulation results with the PSPICE program are provided to validate the functionality of the realized inductor. In addition to establishing the practical operation of the simulator, the measured test results obtained from hardware implementation using readily available integrated chips (ICs) are also included.

An analog correlator based CMOS analog front end with digital gain control circuit for hearing aid devices

In this paper, an analog correlator based analog front end with gain control circuit for hearing aid devices is designed and fabricated with 0.18 $$\upmu \mathrm{m}$$ CMOS process. The proposed analog front end consists of an analog correlator comprised of a multiplier, an integrator, and a mixed mode variable gain amplifier. The analog correlator is utilized to ensure the low input referred noise. A gain control circuit is implemented in variable gain amplifier. Based on the output of piezoelectric microphone, designed gain control circuit automatically sets the gain. The investigated analog front end offers lower noise and wider dynamic range with compact size compared to conventional architecture. It achieves a 42 $$\mathrm{n}V_{rms}$$ input referred noise and 84 dB signal to noise ratio. The total area of the designed analog front end circuit is 386 $$\upmu \mathrm{m}$$ $$\times$$ 569 $$\upmu \mathrm{m}$$ . Designed circuit is interfaced with a sensor model of piezoelectric microphone and its performance is successfully verified against simulation results.

A CMOS Peak Detect and Hold Circuit With Auto-Adjust Charging Current for NS-Scale Pulse ToF Lidar Application

This paper presents a novel CMOS peak detect and hold (PDH) circuit scheme for pulsed time of flight (ToF) Lidar application. The proposed PDH circuit, which is one part of analog front end (AFE) circuit of Lidar receiver, is used to widen the narrow input pulse width, aiming to easily digitize the pulse amplitude through a low-speed and low-cost ADC in pulsed ToF Lidar application. The reset voltage clamped to the common-mode level of the input pulse voltage is beneficial to reduce the pedestal error voltage. Meanwhile, the auto-adjust charging current scheme is employed to decrease the peak error through rejecting the overshoot voltage in the proposed PDH circuit. The circuit was implemented and fabricated in a 65-nm CMOS technology. The proposed PDH circuit can detect the pulse voltage with a pulse amplitude range from ~20 mV to ~500 mV and a minimum pulse width of 5 ns. The measured results show that the maximum absolute and relative errors are less than 16 mV and 4.5%, respectively. The layout area of the proposed PDH circuit is equal to 0.17 × 0.14 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Open-loop digital clock generator based VLSI architecture for electromagnetic interference reduction

Nowadays, the size of the hearing aid devices are reduced to make them invisible and function rapidly. As a result of these factors, an EMI is generated inside the chips. The general working principle of the hearing aid SoC is disrupted by this internal EMI. Thus, an open loop fractional dividers based all-digital clock generator is introduced in the proposed hearing aid SoC. The jitter is reduced by the use of a high resolution digital-to-time converter with its range and duty cycle calibration in background. Also, the nonlinearity of the analog front-end circuit in the proposed hearing aid SoC is reduced by introducing a switching block based dynamic element matching process. Furthermore, an improved noise reduction algorithm is proposed based on pitch based voice activity detector and multiband complex spectral subtraction to improve the performance of the proposed hearing Aid SoC. The proposed hearing aid SoC is designed in an 180 nm CMOS technology. The simulation results show that, integrated jitter of the proposed structure is reduced to 0.9 psrms and it achieves a signal to noise ratio of 89.24 dB. The total power consumption of this hearing aid is only 996 μW for 1.2 V supply that shows the superiority of the proposed work than existing works.

Investigation on Stray-Capacitance Influences of Coaxial Cables in Capacitive Transducers for a Space Inertial Sensor.

Ultra-sensitive inertial sensors are one of the key components in satellite Earth’s gravity field recovery missions and space gravitational wave detection missions. Low-noise capacitive position transducers are crucial to these missions to achieve the scientific goal. However, in actual engineering applications, the sensor head and electronics unit usually place separately in the satellite platform where a connecting cable is needed. In this paper, we focus on the stray-capacitance influences of coaxial cables which are used to connect the mechanical core and the electronics. Specially, for the capacitive transducer with a differential transformer bridge structure usually used in high-precision space inertial sensors, a connecting method of a coaxial cable between the transformer’s secondary winding and front-end circuit’s preamplifier is proposed to transmit the AC modulated analog voltage signal. The measurement and noise models including the stray-capacitance of the coaxial cable under this configuration is analyzed. A prototype system is set up to investigate the influences of the cables experimentally. Three different types and lengths of coaxial cables are chosen in our experiments to compare their performances. The analysis shows that the stray-capacitance will alter the circuit’s resonant frequency which could be adjusted by additional tuning capacitance, then under the optimal resonant condition, the output voltage noises of the preamplifier are measured and the sensitivity coefficients are also calibrated. Meanwhile, the stray-capacitance of the cables is estimated. Finally, the experimental results show that the noise level of this circuit with the selected cables could all achieve 1–2 × 10−7 pF/Hz1/2 at 0.1 Hz.

Implementation of Mixing Sequence Optimized Modulated Wideband Converter for Ultra-Wideband Frequency Hopping Signals Detection

Frequency hopping (FH) communications are widely used in Satcom systems. The latest FH systems have exceeded 3 GHz with hop rates up to 100 000 hops/s. Traditional spectrum sensing systems hardly monitor such signals. Modulated wideband converter (MWC) is an emerging compressive sampling structure applied to sample multiband signals. This article analyses the effects of the nonlinearity of analog devices and proposes an optimization method based on a greedy algorithm for mixing sequences to make reconstruction performance uniform across sub-bands. To correct the errors caused by the nonideality of analog front end circuits between the theoretical sensing matrix and the practical one, we also develop a calibrating method that obtains all the sensing matrix coefficients through a single measurement. In conventional MWC, out-band noise will be blended during reconstruction. Instead of matrix factorization, we reserve signal characters and designed sliding filters to improve narrowband signals reconstruction sensitivities. We produced a four-branch MWC principle prototype for FH signal detection. The sensing bandwidth is 3 GHz, and the sampling rate is 400 MHz, whereas the reconstruction sensitivity is as low as 13-dB in-band signal-to-noise.