A CMOS Peak Detect and Hold Circuit With Auto-Adjust Charging Current for NS-Scale Pulse ToF Lidar Application

Abstract

This paper presents a novel CMOS peak detect and hold (PDH) circuit scheme for pulsed time of flight (ToF) Lidar application. The proposed PDH circuit, which is one part of analog front end (AFE) circuit of Lidar receiver, is used to widen the narrow input pulse width, aiming to easily digitize the pulse amplitude through a low-speed and low-cost ADC in pulsed ToF Lidar application. The reset voltage clamped to the common-mode level of the input pulse voltage is beneficial to reduce the pedestal error voltage. Meanwhile, the auto-adjust charging current scheme is employed to decrease the peak error through rejecting the overshoot voltage in the proposed PDH circuit. The circuit was implemented and fabricated in a 65-nm CMOS technology. The proposed PDH circuit can detect the pulse voltage with a pulse amplitude range from ~20 mV to ~500 mV and a minimum pulse width of 5 ns. The measured results show that the maximum absolute and relative errors are less than 16 mV and 4.5%, respectively. The layout area of the proposed PDH circuit is equal to 0.17 × 0.14 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .