Front-end Circuit Research Articles

Multi-Channel Data Acquisition Card under New Acquisition and Transmission Architecture of High Frequency Ground Wave Radar

It is known that the data acquisition and processing system plays an important role in radar target detection system. In order to meet the requirements of real-time processing and accurate transmission of echo signals in high-frequency ground-wave radar (HFGWR) systems, a new acquisition and transmission framework utilizing the designed acquisition card based on the PCIe (peripheral component interconnect express) has been designed and is presented in this paper. The Xilinx FPGA (Field-Programmable Gate Array) chip Kintex7-XC7K325T is adopted as a hardware carrier in acquisition card. The hardware’s composition, analog front-end circuit, the DMA (Direct Memory Access) transmission, FPGA structure, ADC (Analog-to-Digital Converter) chip, and performance test of this card are showed and discussed. Currently, the acquisition card has been accomplished and applied in the practical system of HFGWR.

Simultaneous Acquisition of Ultrasound and Gamma Signals with a Single-Channel Readout.

We propose an integrated front-end data acquisition circuit for a hybrid ultrasound (US)-gamma probe. The proposed circuit consists of three main parts: (1) a preamplifier for the gamma probe, (2) a preprocessing analog circuit for the US, and (3) a digitally controlled analog switch. By exploiting the long idle time of the US system, an analog switch can be used to acquire data of both systems using a single output channel simultaneously. On the nuclear medicine (NM) gamma probe side, energy resolutions of 18.4% and 17.5% were acquired with the standalone system and with the proposed switching circuit, respectively, when irradiated with a Co-57 radiation source. Similarly, signal-to-noise ratios of 14.89 and 13.12 dB were achieved when US echo signals were acquired with the standalone system and with the proposed switching circuit, respectively. Lastly, a combined US-gamma probe was used to scan a glass target and a sealed radiation source placed in a water tank. The results confirmed that, by using a hybrid US-gamma probe system, it is possible to distinguish between the two objects and acquire structural information (ultrasound) alongside molecular information (gamma radiation source).

A Low Noise 28Gbaud/s Linear PAM4 Receiver Front-End for Optical Communication Applications in 0.13μm BiCMOS Technology

This paper presents a low noise 28 Gbaud/s linear receiver front-end for fourth-order pulse amplitude modulation (PAM4) signal applied in the field of optical communication. The designed receiver front-end includes a transimpedance amplifier(TIA), an automatic gain control (AGC) and a DC offset cancellation (DCOC) circuit. The pseudo-differential structure of the TIA is designed to achieve low noise. The resistance and capacitance degradation technology are introduced in the variable gain amplifier(VGA) and the equalizer(EQ) to improve linearity and optimize the bandwidth. In the AGC mode, the feedback loop controls the output amplitude to be a desired value within a large range of input current. The PAM4 optical receiver front-end achieves a maximum differential transimpedance gain of 76 dBΩ and -3dB bandwidth of 27 GHz. The equivalent input noise current density with the front-end circuit is . In 0.13µm BiCMOS technology, the PAM4 front-end chip consumes 200 mW with a 3.3V voltage supply.

Flexible Complementary Oxide Thin-Film Transistor-Based Inverter With High Gain

Wearable bio-sensing devices are considered promising for ubiquitous heath monitoring. To accurately read out small bio-signals, the development of high-performance flexible front-end circuits is crucial. Oxide semiconductors are considered one of the most promising active channel materials for on-polymeric-foil electronics. In this article, a high-gain flexible complementary metal–oxide–semiconductor (CMOS) inverter with a beta ratio of 1, a desirable feature for device miniaturization, was demonstrated by monolithically integrating a top-gated n-type indium gallium zinc oxide (IGZO) thin-film transistor (TFT) and a bottom-gated p-type SnO TFT on a 5.5- $\mu \text{m}$ -thick polyimide substrate. The influence of atomic layer deposited (ALD)-HfO2 capping layer on the properties of oxide active channels has been analyzed. The flexible inverter exhibited a high static voltage gain of 370 V/V and balanced noise margins (noise margin high of 4.8 V, noise margin low of 4.7 V) for a supply voltage of 10 V. In addition, the voltage transfer characteristics remained virtually unchanged when the device was subjected to an outward or an inward bending radius of 2.5 mm, indicating the complementary oxide-TFT-based inverter is practical for flexible electronics applications.

Analog Front-End Circuits With Input Current Attenuation and Heterodyne Techniques for Low-Cost Phase-Shift LADAR Receiver

Analog front-end (AFE) circuits with wide dynamic range and low walk error for cost-effective phase-shift LADAR receiver are presented in this work. The inverter-based trans-impedance amplifier (TIA) utilized in the proposed AFE has been modified with two additional transistors in its input node, which can attenuate the input current automatically and adjust the bandwidth dynamically. The improved TIA significantly increases the dynamic range of AFE without any complicated gain-control circuits, while keeping the walk error in a low level. Heterodyne techniques are then adopted to modulate the received signals to low-frequency carriers, as well as the driving signal of laser diode, which is modulated with a mirrored voltage-input channel. Thus, systematic errors caused by the uncertainty of the initial phase in transmitted signal can be reduced. As a result, high-accuracy phase detections and range measurements can be realized conveniently by just sampling two low-frequency (~100 kHz in this design) output signals. The AFE circuits have been fabricated in a standard 65-nm CMOS technology with a total chip area of $0.59\times0.68$ mm2 including the IO PADs. The measured power consumption is 24.3 mW with a 2.5-V supply. With a modulated frequency of 30 MHz and a local oscillator frequency of 30.1 MHz, the measured input-referred noise of the proposed AFE is 8.4 nA $_{RMS}$ and the walk error is less than ±1.8% for a wide dynamic range of 500 nA ~ 10 mA. The measurement results show that the proposed AFE can achieve wide dynamic range and low walk error, while the system complexity and cost of the phase-shift LADAR receiver can also be reduced.

Low-Latency Lattice-Reduction-Aided One-Bit Precoding Processor for 64-QAM 4×64 MU–MIMO Systems

Massive multi-user multiple-input multiple-output (MU-MIMO) communication is a crucial technique for next-generation wireless systems because it enables high-throughput and ultra-reliable data transmission. However, high power consumption is a challenging problem in conventional transceiver designs, where each RF chain at the transmitter requires a pair of high-resolution digital-to-analog converters (DACs), which are the primary power sources in front-end circuits. Therefore, quantized precoding algorithms were recently proposed to address this issue. They used low-resolution DACs at the transmitter and compensated for the distortion caused by the quantization effect at the baseband. This paper proposes a constellation-range gain-controlled lattice-reduction-aided (CR-GCLRA) one-bit precoding algorithm for massive MU-MIMO systems with high-order quadrature amplitude modulation (QAM) signaling. Lattice reduction (LR) preprocessing is adopted for performance enhancement. A novel gain-control mechanism is proposed to address the constellation range expansion problem in conventional LR preprocessing. We designed and implemented a CR-GCLRA one-bit precoding processor by using TSMC 40-nm CMOS technology to accelerate the one-bit precoding processing for 64-QAM 4 ×64 MU-MIMO system. The proposed one-bit precoding processor can achieve a throughput of 43.92 Mbits per second at a clock speed of 269 MHz with 271 mW power consumption and 0.51μs latency.

Electrical Impedance Tomography for Biomedical Applications: Circuits and Systems Review

There has been considerable interest in electrical impedance tomography (EIT) to provide low-cost, radiation-free, real-time and wearable means for physiological status monitoring. To be competitive with other well-established imaging modalities, it is important to understand the requirements of the specific application and determine a suitable system design. This paper presents an overview of EIT circuits and systems including architectures, current drivers, analog front-end and demodulation circuits, with emphasis on integrated circuit implementations. Commonly used circuit topologies are detailed, and tradeoffs are discussed to aid in choosing an appropriate design based on the application and system priorities. The paper also describes a number of integrated EIT systems for biomedical applications, as well as discussing current challenges and possible future directions.

Coherent synthesis of ultrashort pulse fiber laser based on balanced difference method

The output power of the fiber laser can be increased by synthesizing the output beam, but the problem of low output power is caused by the poor ability of controlling bandwidth in the current synthesis research. Therefore, a coherent synthesis method of ultrashort pulse fiber laser based on balanced difference method is proposed. The balance difference of fiber combiner is divided into different modules, including data exchange and acquisition, circuit balancing, phase compensation, etc. Select appropriate ad conversion chip, use Ethernet chip W5300, design data exchange, ensure the normal use of data acquisition function, in the signal preprocessing module, use band-pass filter to filter out unnecessary frequency components, use AD603 to design front-end balancing circuit, design signal separation circuit, separate AC and DC signals, use active phase lock. The phase compensation of each laser is realized by the fixed technology, and the coherent synthesis of ultrashort pulse fiber laser is realized by the fiber combiner. The experimental results show that, compared with the traditional coherent synthesis method, the output power of the coherent combination method based on balanced difference method is about 900 kW, which has higher output power and better control bandwidth. It provides a theoretical basis for practical application.

100.5 dB SNDR Analog Front-End With a Resistor-Based Discrete-Time Delta-Sigma Modulator for Eliminating Switching Noise and Harmonics

This paper presents a high-resolution analog front-end (AFE) circuit operating in the 25 kHz signal bandwidth. The AFE consists of a capacitively-coupled chopper instrumentation amplifier (CCIA) and a third-order delta-sigma modulator (DSM). Signal distortion often occurs at the junction of CCIA and DSM, so the resistor-based discrete-time DSM (RB DT–DSM) is proposed to solve this problem. Both conventional DT–DSM and the proposed RB DT–DSM are designed and compared through simulations and chip measurements. When a conventional DT–DSM is used, a switched-capacitor integrator with a large capacitor and switch are connected to the CCIA output node, so large switching noise, significant charge injection, and a long settling time occur at the CCIA output, resulting in harmonic distortions. Therefore, CCIA requires more power consumption to reduce the settling time for conventional DT–DSM architectures. On the other hand, when the proposed RB DT–DSM is used, only a resistor and a small switch are connected to the CCIA output. Due to this novel interface technique, the switching noise is very small at the CCIA output, and the settling of the CCIA becomes fast. As a result, it is possible to effectively eliminate harmonic distortions while reducing the power requirement of the CCIA. Both the conventional and proposed AFE circuits were manufactured by a 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> complementary metal-oxide-semiconductor (CMOS) process. The conventional AFE shows a peak SNR of 101.1 dB and a peak SNDR of 91.2 dB. The proposed AFE with RB DT–DSM shows a peak SNR of 101.3 dB and a peak SNDR of 100.5 dB, which verifies the significant reduction in harmonic distortions.

High-Linearity Front-End Circuit for Remote Grounded Capacitive Sensors

This article presents a novel front-end circuit for remote grounded capacitive sensors. The circuit is insensitive to amplifier input capacitance and stray interconnecting-cable capacitances. It does not rely on neutralization or compensation techniques that require manual adjustments and high-accuracy reference components. The proposed solution reduces the circuit input capacitance below a few femptofarads using a simple but properly shielded custom transformer. In addition, the circuit keeps a nonlinearity error below 0.01% when measuring capacitances of units or tens of picofarad, even with up to 12-m interconnecting cables.

Development of photoelectric integrated single photon avalanche photodiode and front-end circuit based on BCD technology

Development of photoelectric integrated single photon avalanche photodiode and front-end circuit based on BCD technology

Multi-Channel Low-Noise Analog Front Design

With the development of digital nuclear pulse processing technology, the requirements for the analog front-end circuit of digital energy spectrometers are getting higher and higher. Not only need to reduce the noise caused by the device as much as possible, but also need to meet the needs of multi-channel data acquisition. This article based on VGA (Variable Gain Amplifier) has designed a multi-channel low-noise analog front-end circuit to meet the functional requirements of the energy spectrometer while reducing the signal transmission in the analog front-end circuit as much as possible. The circuit noise is strictly controlled to ensure the signal-to-noise ratio of signal transmission. AD9255 is used for waveform digitization, and the input range is 100 μV-2 VPP. After testing, the circuit has a wider gain range and better noise control. Input 100 μVpp signal when the analog front-end gain is 24 dB, and its signal-to-noise ratio can reach 1:1.

Wideband via-Loaded Cylindrical Open-Ended SIW Cavity Antenna

A composite cavity-based antenna is proposed and presented in this work. Three kinds of modes of the composite structure are involved to obtain a wide bandwidth: the ${\mathrm {TE}}_{11 {\scriptstyle {}^{\scriptstyle 1}}\hspace {-0.224em}/\hspace {-0.112em}{\scriptstyle 2} }$ cavity mode of a cylindrical open-ended substrate integrated waveguide cavity, the odd TEM mode generated by loading two rectangular via holes inside the cavity, and the higher-order loop modes (L3 and L5) of a circular ring detached from the cavity by a circumferential slot located at the cavity’s side wall. In the implementation of the antenna, slot coupling feeding methodology is applied, which also introduces a resonance for the bandwidth enhancement. A simulated fractional impedance bandwidth of 57.3% with $|{\mathrm{ S}}_{11}| dB from 24.9 GHz to 44.9 GHz is achieved ( $|{\mathrm{ S}}_{11}|= -9.7$ dB at $f=27.7$ GHz is ignored). The antenna has a broadside radiation pattern within the operating frequency band and a maximum simulated broadside gain of 10.6 dBi at ${f}=27$ GHz. Multi-layer technique and metallized via holes processing, which become commercial nowadays, are two critical techniques of the presented antenna. The simple structure is benefit of the fabrication and the integration with other planar front-end circuits. The antenna is fabricated and experimentally verified. A small difference is observed between the measurement and the simulation. A measured fractional bandwidth of 52% from 27 GHz to 46 GHz ( $|{\mathrm{ S}}_{11}|= -9$ dB at ${f}=29$ GHz is ignored) and a measured maximum broadside gain of 9.5 dBi are achieved.

In Vivo Evaluation of a Subcutaneously Injectable Implant with a Low-Power Photoplethysmography ASIC for Animal Monitoring.

Photoplethysmography is an extensively-used, portable, and noninvasive technique for measuring vital parameters such as heart rate, respiration rate, and blood pressure. The deployment of this technology in veterinary medicine has been hindered by the challenges in effective transmission of light presented by the thick layer of skin and fur of the animal. We propose an injectable capsule system to circumvent these limitations by accessing the subcutaneous tissue to enable reliable signal acquisition even with lower light brightness. In addition to the reduction of power usage, the injection of the capsule offers a less invasive alternative to surgical implantation. Our current prototype combines two application-specific integrated circuits (ASICs) with a microcontroller and interfaces with a commercial light emitting diode (LED) and photodetector pair. These ASICs implement a signal-conditioning analog front end circuit and a frequency-shift keying (FSK) transmitter respectively. The small footprint of the ASICs is the key in the integration of the complete system inside a 40-mm long glass tube with an inner diameter of 4 mm, which enables its injection using a custom syringe similar to the ones used with microchip implants for animal identification. The recorded data is transferred wirelessly to a computer for post-processing by means of the integrated FSK transmitter and a software-defined radio. Our optimized LED duty cycle of 0.4% at a sampling rate of 200 Hz minimizes the contribution of the LED driver (only 0.8 mW including the front-end circuitry) to the total power consumption of the system. This will allow longer recording periods between the charging cycles of the batteries, which is critical given the very limited space inside the capsule. In this work, we demonstrate the wireless operation of the injectable system with a human subject holding the sensor between the fingers and the in vivo functionality of the subcutaneous sensing on a pilot study performed on anesthetized rat subjects.

Performance Analysis for DOA Estimation Using Compressive Measurements With Coprime Frequencies

Exploiting compressive measurements of two signals with coprime carrier frequencies to estimate direction-of-arrivals (DOAs) can obtain a high estimation performance with low system complexity. Coprime carrier frequencies can dramatically reduce the number of sensors, while compressive measurements effectively control the number of front-end circuit chains. However, the corresponding theoretical performance analysis has not been conducted. Therefore, we aim at revealing the estimation performance mathematically in this paper. First, the Cramér-Rao bound (CRB) expression with respect to the DOAs is derived to illustrate the performance limit. Then, the existence condition of the derived CRB expression is obtained, and the number of degrees of freedom (DOFs) is analyzed based on the condition. Finally, the CRB asymptotic properties are explicitly discussed, and it is found that, in the under-determined case, the CRB approaches a constant, which is similar as the asymptotic properties of sparse arrays. Through theoretical analysis in this paper, the superiorities of the proposed scheme are further verified. Specifically, the proposed scheme can obtain a higher estimation performance, including the number of DOFs and estimation accuracy, with the same number of front-end circuit chains than classical structure using coprime frequencies. From the simulation results, 24 targets can be resolved by the proposed scheme with 5 channels, while the classical structure can resolve only 20 targets. Other properties are also examined by numerical simulations.

In-Run Scale Factor Compensation for MEMS Gyroscope Without Calibration and Fitting

This paper presents an in-run scale factor error compensation for the micro-electro-mechanical system (MEMS) gyroscope without system calibration and data fitting. The causes of three scale factor errors (instability, nonlinearity, and asymmetry) are analyzed. Next, the instability and nonlinearity by open-loop detection (Mode I), and closed-loop detection (Mode II) are discussed according to the specific comb capacitance and the front-end detection circuit. The closed-loop detection transfer function is studied, and a series of equivalent conversions are performed to obtain a method (Mode III) for improving the temperature stability of scale factor. The results of the experiment indicated that the nonlinearity and asymmetry of the Mode II and Mode III are increased by 1.8 times and 3.5 times than that of Mode I. Furthermore, the instability of Mode II and Mode III is reduced by 10 times and 19 times over -20°C to 40°C. Besides, the mode III does not affect the static and dynamic performance of gyroscope according to the test results of bias and bandwidth.

An Accurate Circuit Model for the Statistical Behavior of InP/InGaAs SPAD

In the field of near-infrared weak light detection, an InP/InGaAs single-photon avalanche diode (SPAD) is preferred due to the advantages of high sensitivity, low cost and room-temperature operation. To properly simulate and optimize the SPAD’s front-end circuit, a comprehensive and compact behavior model of the InP/InGaAs SPAD is normally required to accurately describe the statistical behavior of the detectors. In this paper, an InP/InGaAs SPAD analytical model is constructed, which not only includes the direct current (DC) and alternating current (AC) behavior simulating the avalanche and quenching processes, but also describes the dark count, after-pulsing and photon detection efficiency. For dark count noise, three important generation mechanisms are considered, including thermal generation, trap-assisted tunneling and band-to-band tunneling. The model described by the Verilog-A hardware description language (HDL) can be directly implemented in the commercial circuit simulator. A gated mode, passive quenching and recharging circuit is used to simulate and verify the developed model. The simulation results are in good agreement with the reported test data, demonstrating the accuracy of the developed InP/InGaAs SPAD model.

External temperature sensor assisted a new low power photoplethysmography readout system for accurate measurement of the bio-signs.

This study presents an external temperature sensor assisted a new low power, time-interleave, wide dynamic range, and low DC drift photoplethysmography (PPG) signal acquisition system to obtain the accurate measurement of various bio signs in real-time. The designed chip incorporates a 2-bit control programmable transimpedance amplifier (TIA), a high order filter, a 3:8 programmable gain amplifier (PGA) and 2 × 2 organic light-emitting diode (OLED) driver. Temperature sensor is used herein to compensate the adverse effect of low-skin-temperature on the PPG signal quality. The analog front-end circuit is implemented in the integrated chip with chip area of 2008 μm × 1377 μm and fabricated via TSMC T18 process. With the standard 1.8 V, the experimental result shows that the measured current sensing range is 20 nA–100 uA. The measured dynamic range of the designed readout circuit is 80 dB. The estimated signal to noise ratio is 60 dB@1 uA, and the measured input referred noise is 60.2 pA/Hz½. The total power consumption of the designed chip is 31.32 µW (readout) + 1.62 mW (OLED driver@100% duty cycle). The non-invasive PPG sensor is applied to the wrist artery of the 40 healthy subjects for sensing the pulsation of the blood vessel. The experimental results show that for every 1 °C decrease in mean ambient temperature tends to 0.06 beats/min, 0.125 mmHg and 0.063 mmHg increase in hear rate (HR), systolic (SBP) and diastolic (DBP), respectively. Similarly, for every 1 °C increase in mean ambient temperature tends to 0.13 beats/min, 0.601 mmHg and 0.121 mmHg increase in HR, SBP and DBP, respectively. The measured accuracy and standard error for the HR estimation are 96%, and − 0.022 ± 2.589 beats/minute, respectively. The oxygen stauration (SpO2) measurement results shows that the mean absolute percentage error is less than 5%. The resultant errors for the SBP and DBP measurement are − 0.318 ± 5.19 mmHg and − 0.5 ± 1.91 mmHg, respectively.Electronic supplementary materialThe online version of this article (10.1007/s00542-020-05106-y) contains supplementary material, which is available to authorized users.

A 32-GS/s Front-End Sampling Circuit Achieving &gt;39 dB SNDR for Time-Interleaved ADCs in 65-nm CMOS

This paper presents a 32-GS/s front-end sampling circuit (FESC) in 65-nm CMOS. The FESC is designed for a 32-channel time-interleaved analog-to-digital converter (ADC), and the [Formula: see text] two-stage interleaving structure leads to a good trade-off between bandwidth and linearity. The analysis and cancellation of charge injection, clock feedthrough, and signal feedthrough are presented. Inductor peaking technique is adopted to extend the bandwidth of the buffer between the first and the second stage. Based on the simulation results, the proposed FESC consumes 136[Formula: see text]mW at 32 GS/s, and the signal-to-noise ratio (SNDR) is up to 39.55 dB at Nyquist input, achieving a state-of-the-art power efficiency.

Noise Analysis of Charge-Balanced Readout Circuits for MEMS Accelerometers

This work presents an approach for a complete noise analysis and optimization flow for switched-capacitor MEMS readout frontend circuits. The flow starts with an early noise evaluation on a high abstraction level. The evaluation is performed using analytical calculations as well as simulations in MATLAB/Simulink. The presented approach is applied to a charge-balanced readout circuit example, which is eventually simulated at transistor level and measured. The results of the analytical calculations, the Simulink and the transistor-level simulations as well as the measurements are then compared showing the accuracy of the approach. Furthermore, an analysis is carried out on how to decrease the noise by identifying the most impacting parameters of the circuit and by evaluating the influence of a boxcar sampler in the charge-balanced readout circuit.