Front-end Chip Research Articles

Monitoring electron and proton beam profiles with segmented silicon sensors

The FRIDA INFN project characterized thin silicon sensors for monitoring electron FLASH beams, showing a response linearity up to ∼10 Gy/pulse on 9 MeV electrons. The use of segmented silicon configurations could provide the spatial resolution useful in Spatially Fractionated Radiotherapy (SFRT). Within the MIRO INFN project, a strip sensor integrated with a multichannel readout chip is being developed and tested for monitoring FLASH and SFRT electron and proton beams. One hundred and twenty-eight strips are independently read by two front-end TERA chips. Preliminary tests were performed on 6–10 MeV electron beams at the LINAC at Physics Department of the University of Torino, with and without using a tungsten minibeam collimator, and on 62–226 MeV proton beams at CNAO (Pavia). The capability to spatially resolve electron and proton beams at conventional dose-rates has been proved.

A real-time cardiac output monitoring system based on photoplethysmography

Abstract Cardiac output is a critical parameter for assessing the cardiovascular system, and thermodilution is commonly used as CO monitoring in clinical settings. Thermodilution cannot be applied in continuous monitoring due to invasion. Photoplethysmography signal originates from the cardiovascular system. We proposed a CO continuous monitoring system based on photoplethysmography and deep learning method. PPG waveform parameters are extracted during the pre-processing stage, and fed into the deep learning model to calculate cardiac output. The system employs an analog front-end chip and an HPS_FPGA architecture to capture PPG signals. The pre-processing and the deep learning model-driven algorithm are designed in Python on the custom Linux for HPS. It realizes the real-time processing of the PPG signals and the continuous monitoring of cardiac output. Validated by an FPGA, the system reported average cardiac output monitoring results of approximately 5.09 L/min at rest and about 7.39 L/min after exercise.

Characterisation studies of two front-end electronics chips designed for SiPM readout

A new front-end ASIC named ”PIST” (pico-second timing) has been successfully developed using 55 nm CMOS technology for the silicon photomulplier (SiPM) readout with a single channel with a major aim of fast timing. We performed extensive tests to evaluate the timing performance of a dedicated test stand equipped with a PIST chip. The results show that the system timing resolution can reach sub 10 ps for large SiPM signals, while the PIST intrinsic timing resolution is better than 5 ps. The PIST dynamic range has been further extended using the time-over-threshold (ToT) technique. Meanwhile, we fully characterised a new commercially available SiPM-readout 32-channel ASIC for developments of future high-granularity crystal calorimetry, including the single photon calibration and the dynamic range of different gain regions. Other promising potentials include fast timing resolution, fast readout speed and low power dissipation. Comprehensive measurements were made with a laser beam and high-energy particle beams with crystals and SiPMs. First testing results show that this chip has an excellent signal-to-noise and a large dynamic range. This contribution will introduce the ASICs as well as dedicated test stands and also present highlighted results including the timing resolution, single photon calibration and dynamic range.

Redundant series cell voltage measurement circuit design of battery management system for functional safety

In most battery management system (BMS) circuit designs, the analog front end (AFE) chip is used to get the series cell voltage of the battery pack. However, it can lead to incorrect calculations by the BMS, causing errors in battery information, failures in protection control, and triggering a battery system fire accident if the AFE chip is abnormal. Unfortunately, the BMS will never know the correct of measured results if it is measured by a single AFE chip. This paper proposes a redundant series voltage measurement system (RSVMS) for the series cell voltage of the battery pack. The original AFE is referred to as the main AFE (m-AFE). The RSVMS can be regarded as redundant AFE (r-AFE). In this paper, the r-AFE consists of a series cell selector and an analog-to-digital (ADC) converter with an isolated communication function to transmit measurement results to the microcontroller unit (MCU) of the BMS. Due to the hardware requirements of functional safety, it does not allow using two identically designed hardware as redundant systems. To satisfy the hardware level of functional safety and to minimize the hardware cost and size, the series cell selector of r-AFE shares the same hardware circuit as the Active Hybrid Equalizer Circuit (A-HEC). The cell selector of A-HEC is composed of the back-to-back MOSFET switch array with a simple ON/OFF function. The MCU of BMS will identify the abnormal of voltage measurement results when the difference of m-AFE and r-AFE is over the threshold. In summary, r-AFE can ensure the accuracy of cell voltage measurement for m-AFE to avoid significant errors when estimating battery information and avoid disaster caused by failure or malfunction of protection functions. In addition, the m-AFE and r-AFE are two independent designs to avoid similar errors caused by identical circuit configurations.

Embedded FPGA developments in 130 nm and 28 nm CMOS for machine learning in particle detector readout

Embedded field programmable gate array (eFPGA) technology allows the implementation of reconfigurable logic within the design of an application-specific integrated circuit (ASIC). This approach offers the low power and efficiency of an ASIC along with the ease of FPGA configuration, particularly beneficial for the use case of machine learning in the data pipeline of next-generation collider experiments. An open-source framework called “FABulous” was used to design eFPGAs using 130 nm and 28 nm CMOS technology nodes, which were subsequently fabricated and verified through testing. The capability of an eFPGA to act as a front-end readout chip was assessed using simulation of high energy particles passing through a silicon pixel sensor. A machine learning-based classifier, designed for reduction of sensor data at the source, was synthesized and configured onto the eFPGA. A successful proof-of-concept was demonstrated through reproduction of the expected algorithm result on the eFPGA with perfect accuracy. Further development of the eFPGA technology and its application to collider detector readout is discussed.

A first look at AS-ROC: a Si-Ge integrated chip readout for fast timing

Advances in timing detector technology require new specialized readout electronics. Applications demand below 10 ps time of arrival resolution and low power for a low repetition rate. A possible path to achieve O(10 ps) time resolution is an integrated chip using Silicon Germanium (SiGe) technology. Using DoE SBIR funding, Anadyne, Inc., in collaboration with UC Santa Cruz, has developed a prototype SiGe front-end readout chip optimized for low power and timing resolution. Two versions of the chip were produced with performance in simulation: a more power version with 10 ps resolution at 5 fC with 1.1 mW/channel, and a less power version with 10 ps resolution at 8 fC with 0.6 mW/channel.The chip was produced at Tower Semiconductor with 350 nm technology. The ASIC from the prototype run shows good performance: a rise time of 0.7–1 ns and 25 mV per fC response with RMS noise <1 mV. Simulation and results from the prototype will be reported in this paper.

Design and preliminary test results of the charge sensitive amplifier for gain-less charge readout in high-pressure TPC

This paper presents the design and electrical test results of a low-noise front-end chip (named Topmetal-S) in a High-pressure Time Projection Chamber (TPC) for searching the neutrinoless double beta decay. The Topmetal-S has been fabricated in a 130 nm CMOS technology. The proposed front-end chip consists of a charge collection electrode, a Charge Sensitive Amplifier (CSA) and peripheral circuits. The test results indicate that the CSA features an input linear dynamic range of approximately 6.64 fC, a charge-conversion gain of about 220 mV/fC and an Equivalent Noise Charge (ENC) of approximately 115 e - after a digital trapezoidal pulse shaper.

First experimental validation of silicon-based sensors for monitoring ultra-high dose rate electron beams

Monitoring Ultra-High Dose Rate (UHDR) beams is one of the multiple challenges posed by the emergent FLASH radiotherapy. Technologies (i.e., gas-filled ionization chambers) nowadays used in conventional radiotherapy are no longer effective when applied to UHDR regimes, due to the recombination effect they are affected by, and the time required to collect charges. Exploiting the expertise in the field of silicon sensors’ applications into clinics, the medical physics group of the University and INFN Torino is investigating thin silicon sensors as possible candidates for UHDR beam monitoring, exploiting their excellent spatial resolution and well-developed technology. Silicon sensors of 30 and 45 µm active thicknesses and 0.25, 1 and 2 mm2 active areas were tested at the SIT ElectronFlash machine (CPFR, Pisa) on 9 MeV electron beams, featuring a pulse duration of 4 µs, a frequency of 1 Hz, and a dose-per-pulse ranging from 1.62 to 10.22 Gy/pulse. The silicon sensors were positioned at the exit of the ElectronFlash applicator, after a solid water build-up slab, and were readout both with an oscilloscope and with a multi-channel front-end readout chip (TERA08). A response linearity extending beyond 10 Gy/pulse was demonstrated by comparison with a reference dosimeter (FlashDiamond), thus fulfilling the first requirement of a potential application in UHDR beam monitoring.

Reliability studies of the custom-designed front-end and ADC chips used for JUNO large photomultipliers electronics

Reliability studies of the custom-designed front-end and ADC chips used for JUNO large photomultipliers electronics

Radiation Detector Front-End Readout Chip with Nonbinary Successive Approximation Register Analog-to-Digital Converter for Wearable Healthcare Monitoring Applications.

A 16-channel front-end readout chip for a radiation detector is designed for portable or wearable healthcare monitoring applications. The proposed chip reads the signal of the radiation detector and converts it into digital serial-out data by using a nonbinary successive approximation register (SAR) analog-to-digital converter (ADC) that has a 1-MS/s sampling rate and 10-b resolution. The minimum-to-maximum differential and integral nonlinearity are measured as -0.32 to 0.33 and -0.43 to 0.37 least significant bits, respectively. The signal-to-noise-and-distortion ratio and effective number of bits are 57.41 dB and 9.24 bits, respectively, for an input frequency of 500 kHz and a sampling rate of 1 MS/s. The SAR ADC has a 38.9-fJ/conversion step figure of merit at the sampling rate of 1 MS/s. The proposed chip can read input signals with peak currents ranging from 20 to 750 μA and convert the analog signal into a 10-bit serial-output digital signal. The input dynamic range is 2-75 pC. The resolution of the peak current is 208.3 nA. The chip, which has an area of 1.444 mm × 10.568 mm, is implemented using CMOS 0.18-μm 1P6M technology, and the power consumption of each channel is 19 mW. This design is suitable for wearable devices, especially biomedical devices.

GPS-Free Wireless Precise Positioning System for Automatic Flying and Landing Application of Shipborne Unmanned Aerial Vehicle.

This research is dedicated to developing an automatic landing system for shipborne unmanned aerial vehicles (UAVs) based on wireless precise positioning technology. The application scenario is practical for specific challenging and complex environmental conditions, such as the Global Positioning System (GPS) being disabled during wartime. The primary objective is to establish a precise and real-time dynamic wireless positioning system, ensuring that the UAV can autonomously land on the shipborne platform without relying on GPS. This work addresses several key aspects, including the implementation of an ultra-wideband (UWB) circuit module with a specific antenna design and RF front-end chip to enhance wireless signal reception. These modules play a crucial role in achieving accurate positioning, mitigating the limitations caused by GPS inaccuracy, thereby enhancing the overall performance and reception range of the system. Additionally, the study develops a wireless positioning algorithm to validate the effectiveness of automatic landing on the shipborne platform. The platform's wave vibration is considered to provide a realistic landing system for shipborne UAVs. The UWB modules are practically installed on the shipborne platform, and the UAV and the autonomous three-body vessel are tested simultaneously in the outdoor open water space to verify the functionality, precision, and adaptability of the proposed UAV landing system. Results demonstrate that the UAV can autonomously fly from 200 m, approach, and automatically land on the moving shipborne platform without relying on GPS.

Thermal and supply voltage analysis of optimized ring oscillator for pixel detector readout chip

This paper provides a specific study of the upgrade of the ATLAS pixel detector in preparation for the upgrade of the Large Hadron Collider (LHC). The upgrade to High Luminosity-LHC (HL-LHC) is expected to start after the long shutdown in 2025-2027. The scheduled upgrade for ATLAS will be able to efficiently cope with the challenges caused by the high luminosity imposed by the HL-LHC. A new full-silicon Detector Inner Tracker (ITk) will replace the current ATLAS Inner Detector (ID). The ITk pixel detector will consist of more layers than in the current pixel detector. This study focuses on the Ring Oscillator (ROSC) sensors embedded in the ITkPix-V1 Front-End chip of the ATLAS ITk pixel detector. The paper reports the frequency response of the ROSC at various temperatures and voltage supply values. The results showed a high sensitivity of ROSCs frequencies to the applied voltage and the external temperatures which indicates the reliability of the ITkPix-V1 chip for the future ITk pixel modules.

SystemC framework for architecture modelling of electronic systems in future particle detectors

The prototyping cost in advanced technology nodes and the complexity of future detectors require the adoption of a system design approach common in the industry: design space exploration through high-level architectural studies to achieve clear and optimized specifications.This contribution proposes a configurable SystemC framework to simulate the readout chain from the front-end chips to the detector back-end. The model is transaction accurate, includes an event generator, interfaces with real physics events, and provides metrics such as readout efficiency, latency, and average queue occupancy.This contribution details the structure of the framework and describes a case study based on the LHCb VeLo upgrade II.

A Low-Power V-Band Radar Transceiver Front-End Chip Using 1.5 V Supply in 130-nm SiGe BiCMOS

Energy-efficient, low-voltage, and low-power millimeter-wave (mm-wave) radars are gaining increasing attention for battery-powered commercial applications. In this article, the design of a low-power <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> -band radar sensor based on a transceiver (TRX) front-end chip using 1.5 V supply in an advanced SiGe BiCMOS technology with 300 GHz <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{f}\textsubscript{T}$</tex-math> </inline-formula> and 500 GHz <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{f}\textsubscript{max}$</tex-math> </inline-formula> is presented. The monostatic front-end chip utilizes low-voltage low-power circuit-level design techniques to achieve measured 9-dBm transmitter (TX) output power and 27-dB receiver (RX) gain with a simulated 3.8-dB noise figure (NF) consuming a total of only 72 mW in continuous mode. The TRX chip is used to build a radar sensor, which is experimentally verified in an anechoic chamber. The low-power sensor achieves a 46-dB dynamic range and a ranging precision better than 3.4 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula> m measured with a static target at 1 m. Phase measurements using the low-power radar in the continuous-wave (CW) mode demonstrate that submillimeter movements can be tracked, and notably main vital parameters of a human can be determined accurately. Experimental results show that the performance of the proposed low-power TRX front-end chip is very competitive with designs in modern CMOS technologies.

Simulation and discussion of typical radio frequency filters

The demand for filters is increasing as the frequency bands for 5G expand. RF filters become the segment with the largest market share of RF front-end chips. More crowded frequency bands, as well as thinner and lighter communication equipment, necessitate higher filter performance. In this paper, several technologies for the implementation of Radio Frequency filter are presented. Essentially three types are considered: (i) Lumped Element (LC) Filter and Integrated Passive Devices (IPD) technology; (ii) Acoustic Wave Filter; and (iii) a composite filter design that combines acoustic and IPD technologies. Benefits and drawbacks of these diverse configurations in terms of their technical performance and current applications are examined, and several models are presented and simulated using ADS software.

Single Antenna and No Circulator Full-Duplex With 52 dB Wideband Self-Interference Suppression

Full-duplex (FD) enables high spectrum efficiency and dynamic spectrum accessing, although its application is restricted by significant self-interference. In this work, we present an integrated, single antenna, wideband FD self-interference suppression front-end solution, targeting for short-range wireless communication. Based on the characteristic of bi-directional signal transparency of N-phase passive mixer, a mixer-first active electrical balance self-interference suppression architecture is proposed. As no costly and space-consuming out-of-chip circulator is needed, compared with traditional single antenna suppression solutions, it is attractive for cost and area saving In addition, to alleviate the multi-path effect, a two-tap baseband self-interference suppression is adopted, which also helps broaden the self-interference suppression bandwidth. The fabricated FD front-end chip, employing 180nm CMOS process, has a noise figure (NF) of 8.6dB, and at the maximum TX power, the NF is degrade by 4.9dB. Test results show the achieved self-interference suppression depth is up to 52dB over 30MHz, with a much smaller antenna interface and chip size which is 0.75 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> , compared with other dual and signal antenna solutions. The wireless communication function of the propose FD front-end has been verified and the operation carrier frequency range is 0.4-1.2GHz.

Technological sustainable materials and enabling in semiconductor memory industry: A review

This paper provides an overview of current and future deployment of recyclable direct materials and sustainable materials through recycling of interconnect metals used in semiconductor assembly and packaging. Also, with the aim to study the key technical barriers, challenges of deployment and its reliability performance of impacts of sustainable materials used in semiconductor device packaging, this paper lays out the importance of noble metals and polymeric materials in terms of its materials sustainability for the next decade. This article briefly reviews key aspects of recycled materials reliability concerns, deployment of recycled gold (Au) wire, recycled copper (Cu), and other noble metals in semiconductor packaging and assembly. Frontend chip fabrication sustainability issues and their corresponding countermeasures are covered in this review article as well.

Design of analog front-end integrated circuit of tactile sensor for human-machine interface

—In this paper, a highly integrated analog front-end chip for sensor data acquisition and readout is designed, which is applied to a pressure-to-capacitance-conversion 16 × 16 tactile sensor array. In this design, a 16-channel capacitance-to-digital converter using a combination of op-amp-based Capacitance-Voltage Converter (CVC) and column-parallel Single-Slope Analog-to-Digital Converter (SS ADC) converters has been implemented, increasing the readout speed of the sensor array and saving the chip area. In addition, a sequence of scanning circuit suitable for the 16 × 16 array is proposed, so that the CVC and column-parallel SS ADCs are in a pipelined working mode, which further improves the speed of data conversion and readout. The integrated circuit (IC) is designed and taped out in a 0.18-μm CMOS process technology. The measurement results show that the chip can reach the capacitance detection range from 1 pF to 9.1 pF, and it achieves a detection accuracy of 9 fF under 10-bit ADC quantization. Under the clock frequency of 64 MHz, the refresh rate of the entire array is 3906 fps, and the overall power consumption of the front-end IC is 7.5 mW.

Hybrid SiC Pixel Detector for Charged-Particle Beam Monitor

We report on the hybrid SiC pixel detector for charged-particle beam monitors in high-energy physics experiments. To demonstrate comparable performances of the state-of-the-art Si pixel detectors, SiC pixel sensors with a die size of 25 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> were fabricated based on the p-n diode structure. We combined 12 × 12 diodes of a pixel size of 160 μm and 270 μm pitch with the dedicated readout ASIC by In/Au stud-bump technology. The front-end chip was designed in 0.35 μm CMOS technology, with consideration of a hybrid configuration. Each pixel circuit consists of a charge-sensitive amplifier and band-pass filter, optimized for the SiC sensor. The low noise performance achieved an equivalent noise charge of 55 ± 5e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">–</sup> (rms). The spectrum of <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">241</sup> Am shows an energy resolution of 1.72 keV (FWHM) at 17.8 keV γ-rays at room temperature. The obtained image with <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">90</sup> Sr is a proof of a single MIP detection capability with all pixels. Those results prospect a future application of the SiC pixel sensors to high-intensity proton extinction monitors in the COMET muon experiment at Japan Proton Accelerator Research Complex.

A Charge Sensitive Amplifier in a 28 nm CMOS Technology for Pixel Detectors at Future Particle Colliders

This paper is concerned with the design of a Charge Sensitive Amplifier (CSA) in a 28 nm CMOS technology. The CSA discussed in this work is conceived for High Energy Physics (HEP) experiments at next-generation colliders, where pixel detectors will be read out by specific front-end chips, typically including a CSA exploited for charge-to-voltage conversion of the signal delivered by the sensor. The main analog performance parameters of the CSA, also referred to as the pre-amplifier, are assessed here by means of specific Spectre simulations, which are meant to evaluate the behavior of the analog processor in terms of noise, linearity and capability to compensate for very large detector leakage currents. Noise simulations revealed an equivalent noise charge close to 75 electrons rms for typical operating conditions. Up to 50 nA sensor leakage current can be compensated for thanks to the CSA Keummenacher feedback network. The total current consumption of the CSA is close to 2.2 µA, which, together with a power supply of 0.9 V, translates to a power consumption of 2.0 µW.