Front-end Amplifier Research Articles

NPN Sziklai pair small-signal amplifier for high gain low noise submicron voltage recorder

Small signal-to-noise ratio (SNR) and multiple noise sources, coupled with very weak signal amplitudes of bio signals make brain-computer interface (BCI) application studies a challenging task. The front-end recorder amplifiers receive very-weak signal (few μV) from high impedance electrodes and for efficient processing of such weak and low frequency (<1 kHz) signals a high gain amplifier with very low operating voltage and low total harmonic distortion (THD) is required. Existing amplifiers suffer from problem of high non-linearity and low common mode rejection. A good sense amplifier at predeceasing stage can solve this problem. Utilizing very high amplification factor of Sziklai Pair, this paper proposes two circuit topologies of common-emitter and common-collector negative-positive-negative (NPN) Sziklai Pair small signal amplifiers suitable for use in preamplifier stages of such signal acquisition circuit. Present study provides broad-spectrum of analysis of these amplifiers covering effect of additional biasing resistance RA, variation of ‘ideal forward maximum beta’ β, temperature dependency, noise sensitivity and phase variation. The tunable capability of first topology makes it a suitable candidate in wide variety of other applications. The first amplifier operates on very low input voltage range (0.1μV-6mV) whereas the second amplifier works on 100 μV-11 mV range of input voltage.

Spectrum1k — integrated circuit for medical imaging designed in CMOS 40 nm

We present a multichannel integrated circuit of pixel architecture designed in CMOS 40 nm technology. The chip is composed of 40 × 24 pixels of 75 µm pitch working in the single photon counting mode, each built of front-end amplifier, peak and hold detector, 6-bit analog to digital converter, and memory composed of 64 × 12-bit counters. Thanks to the proposed functionality it is possible to store in each pixel separately information of incoming particles energy spectrum. The chip is dedicated to operating with both electrons and holes of 2.2 ke−–35 ke− energy range. The IC occupies an area of 2 × 4.5 mm2, is already back from fabrication, and is under preliminary measurements.

Design of a high precision converter for multi-sensor information fusion

The converter is a measuring device and is used together with the displacement sensor. In view of the existing sensor transform device is susceptible to error and temperature drift effects acquisition accuracy is not high, we design a high precision transducer, multi-sensor information fusion for vehicle steering gear shaft angular displacement signal measurement, signal transformation and digital transmission. The converter has the characteristics of high precision, miniaturization and low cost. Multi-sensor information fusion high-precision converter adopts front-end signal amplifier circuit, following filter processing circuit and embedded software of microprocessor for online compensation to satisfy the requirements of high-precision transformation. The microcontroller is used as the main control chip to meet the requirements of 8-channel bipolar analog signal acquisition. Two 14-bit, 6-channel A/D chips are used to convert the bipolar analog signal in the range of ±10V, and the RS422 hardware interface circuit performs digital transmission according to the time sequence specified by the central programmer. The experimental results show that the conversion accuracy of the device can reach 0.06%, the digital signal transmission is stable, and it can be widely used in industrial production.

Research on the phase-frequency relationship of the field effect amplifier front-end of shipborne USB system

Normally, most researches on phase calibration of shipborne USB system focus on the means of phase calibration. This article starts with the research on the channel of the system. The composition of the channel is introduced, and the characteristics of the channel is analyzed. Taking the channel of the field effect amplifier front-end as the research object, a mathematical fitting algorithm is used to derive the functional relationship between the phase of the field effect amplifier front-end and the working frequency. The actual calibration data is used for simulation analysis to obtain the fitting order of the function. Combining the phase-frequency relationship of the field effect amplifier front-end and the microwave self-checking phase correction of the field effect amplifier back-end, a new phase calibration method is proposed.

A front-end amplifier with tunable bandwidth and high value pseudo resistor for neural recording implants

In this paper, a tunable front-end amplifier is presented for neural recording implants. To program the low cut-off frequency, a bias circuit is used to adjust the value of pseudo resistors with lower sensitivity to the process variations and also to achieve very large value about 1 TΩ with high linearity. The band pass filter (BPF) can adjust high cut-off frequency and power consumption with two recording modes. The high cut-off frequency is 4.15 kHz and 8.2 kHz in low recording (LR) and high recording (HR) modes, respectively. The low cut-off frequency can be adjusted to 0.8 Hz and 300 Hz. The proposed amplifier is able to separate the neural signals with different frequencies for amplification. It has been designed and simulated in TSMC 0.18 μm CMOS process. The achieved input-referred noise is about 2.1 μVrms and 1.7 μVrms in HR and LR modes, respectively. The total power consumption is 3.6 μW from a 1-V supply with −46.3 dB THD.

Vernier time-to-digital converter with ring oscillators for in-pixel time-of-arrival and time-over-threshold measurement in 28 nm CMOS

The paper describes a design of a prototype chip in 28 nm CMOS technology, consisting of 8 × 4 pixels with 50 μm pitch, dedicated for the precise measurement of Time-of-Arrival (ToA) and Time-over-Threshold (ToT) with a resolution within the picosecond range. To address this requirement, in-pixel Vernier time-to-digital converter (TDC) has been implemented, which utilizes two ring oscillators per pixel. Overall chip architecture is introduced as well as pixel architecture and selected simulation results. The pixel consists of a recording channel and TDC part. The recording channel is composed of an inverter-based front-end amplifier with Zimmerman feedback, a discriminator, a calibration block and a threshold setting block. TDC part includes two ring oscillators together with their calibration blocks and additional logic with counters/shift registers that allow for precise ToA measurement (using Vernier method) as well as ToT measurement (using one of the oscillators). Alternatively, single photon counting (SPC) mode can be used. Frequency of oscillators is set in three steps. First, two global 8-bit digital-to-analog converters (DACs) are used for initial setting of all ring oscillators. Then, per-oscillator capacitance bank and 6-bit DAC are used for fine setting. Simulation results of core blocks suggest that the ToA resolution on the order of tens of picoseconds may be achieved. The chips are already fabricated and are currently being prepared for measurements.

Energy Optimization for Optical Receivers Based on a Cherry-Hooper Emitter Follower Transimpedance Amplifier Front-end in 130-nm SiGe HBT Technology

We present an interpretation of conventional figure-of-merit (FOM) and average input-referred noise current density (IRNCD) that characterizes optical receivers to determine how technologies and circuits best address energy efficiency. A design methodology is presented for differential optical receivers based on Cherry-Hooper Emitter Follower (CHEF) front-end designs targeting 56-Gbps applications is realized in a 130-nm SiGe BiCMOS process. The electrical measurements in a 50- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\Omega$</tex-math></inline-formula> environment demonstrate data rates up to 112 Gbps and 84 Gbps for two design variants. In an open input and maximum gain configuration, the rms input referred noise currents are 3.59 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\mu$</tex-math></inline-formula> <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$A_{RMS}$</tex-math></inline-formula> and 2.41 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\mu$</tex-math></inline-formula> <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$A_{RMS}$</tex-math></inline-formula> and the corresponding average input referred noise current densities are 17.25 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$pA/\sqrt{Hz}$</tex-math></inline-formula> and 12.86 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$pA/\sqrt{Hz}$</tex-math></inline-formula> . The packaged electro-optical measurements of the receiver variants is carried out with a single commercial off-the-shelf (COTS) photodetector demonstrate open eyes at data rates up to 64 Gbps. At 60 Gbps, the receiver variants achieve a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$BER &lt; 10^{-10}$</tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$BER &lt; 10^{-9}$</tex-math></inline-formula> . The total power consumption for the variants are 162 mW and 138 mW for overall energy efficiencies (with respect to electro-optical performance) of 2.53 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$pJ/bit$</tex-math></inline-formula> and 2.3 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$pJ/bit$</tex-math></inline-formula> .

Extending OTDR Distance Span by External Front-End Optical Preamplifier

Optical time-domain reflectometer (OTDR) is used to characterize fiber optic links by identifying and localizing various refractive and reflective events such as breaks, splices, and connectors, and measuring insertion/return loss and fiber length. Essentially, OTDR inserts a pulsed signal into the fiber, from which a small portion that is commonly referred to as Rayleigh backscatter, is continuously reflected back with appropriate delays of the reflections expressed as the power loss versus distance, by conveniently scaling the time axis. Specifically, for long-distance events visibility and measurement accuracy, the crucial OTDR attribute is dynamic range, which determines how far downstream the fiber can the strongest transmitted optical pulse reach. As many older-generation but still operable OTDR units have insufficient dynamic range to test the far-end of longer fibers, we propose a simple and cost-effective solution to reactivate such an OTDR by inserting a low-noise high-gain optical preamplifier in front of it to lower the noise figure and thereby the noise floor. Accordingly, we developed an appropriate dynamic range and distance span extension model which provided the exemplar prediction values of 30 dB and 75 km, respectively, for the fiber under test at 1550 nm. These values were found to closely match the dynamic range and distance span extensions obtained for the same values of the relevant parameters of interest by the preliminary practical OTDR measurements conducted with the front-end EDFA optical amplifier, relative to the measurements with the OTDR alone. This preliminary verifies that the proposed concept enables a significantly longer distance span than the OTDR alone. We believe that the preliminary results reported here could serve as a hint and a framework for a more comprehensive test strategy in terms of both test diversification and repeating rate, which can be implemented in a network operator environment or professional lab.

The Strip SiPM: a study of single photon time resolution

The Strip Silicon PhotoMultiplier (SiPM) allows a photosensitive area to be created that has excellent time resolution coupled to good position resolution. However, as the SiPM is made larger it becomes more difficult to extract the signal produced by a single photon; we thus are using the NINO ASIC as the front-end amplifier. The NINO ASIC dissipates 40 mW of heat per channel. SiPMs are sensitive to temperature; increasing the temperature leads to higher noise and a higher breakdown voltage. For the best timing performance the front-end electronics should be mounted as close to the SiPM as possible; however if, for example, the front-end electronics are mounted on the backside of the SiPM, it would be very difficult to control the temperature of the SiPM. Given this, we chose to mount the NINO ASIC on the printed circuit board (PCB) away from the strip SiPM so that a cooling system can be added. We present here the performance of an array of 16 strip SiPMs readout by 4 NINO ASICs coupled by ∼5 cm of PCB track length. The performance has been evaluated by the measurement of the Single Photon Time Resolution (SPTR) and also the position resolution along the strip determined from the time difference of the signals at each end.

Single-Photon Detection Module Based on Large-Area Silicon Photomultipliers for Time-Domain Diffuse Optics

Silicon photomultipliers (SiPM) are pixelated single-photon detectors combining high sensitivity, good time resolution and high dynamic range. They are emerging in many fields, such as time-domain diffuse optics (TD-DO). This is a promising technique in neurology, oncology, and quality assessment of food, wood, and pharmaceuticals. SiPMs can have very large areas and can significantly increase the sensitivity of TD-DO in tissue investigation. However, such improvement is currently limited by the high detector noise and the worsening of SiPM single-photon time resolution due to the large parasitic capacitances. To overcome such limitation, in this paper, we present two single-photon detection modules, based on 6 × 6 mm2 and 10 × 10 mm2 SiPMs, housed in vacuum-sealed TO packages, cooled to −15 °C and −36 °C, respectively. They integrate front-end amplifiers and temperature controllers, being very useful instruments for TD-DO and other biological and physical applications. The signal extraction from the SiPM was improved. The noise is reduced by more than two orders of magnitude compared to the room temperature level. The full suitability of the proposed detectors for TD-DO measurements is outside the scope of this work, but preliminary tests were performed analyzing the shape and the stability of the Instrument Response Function. The proposed modules are thus fundamental building blocks to push the TD-DO towards deeper investigations inside the body.

WITHDRAWN: Design and implementation of CMOS transimpedance amplifier as a photodetector

Radiation hard electronics, which are required for new fundamental science research, are important to provide reliable diagnostics for fast radiation detection. Transimpedance amplifiers are required in the case of radiation detection to increase low photodetector signals reliably to readable levels. This study explores a way of designing a CMOS transimpedance amplifier (TIA) as a front-end amplifier for the first stage. In fast-neutron scintillation experiments the TIA should be mounted on the silicon photomultiplier (SiPM), which carries up to 1015 n/cm of high-speed neutrons within 0.1–20 MeV. The proposed TIA was developed with “ON's C5 process” (a 600 nm CMOS process). It has a ~300 kΩ gain, bandwidth is at least 250 MHz, the noise is less than 5 pA/ /√Hz, and the output is 1.5–2 V and the power consumption is less than 25 mW. The TIA is expected to sustain reliable performance (<50%) up to a total integrated fluence of 1015 n/cm2. Neutron damage is mainly knock out atoms that cause cascades of displaced atoms and trap creation in SiO2 passivation layers and is not problematic as it is in ionizing radiation and not taken into account in this investigation. Therefore, a design of a transimpedance amplifier with the capacity to amplify low current from a SiPM, with a fast-transient response for single-photon detection and with high radiation hardness for reliable performance under fast neutron irradiation was designed and simulated.

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A Bidirectional Neural Interface SoC With Adaptive IIR Stimulation Artifact Cancelers.

We present a 180-nm CMOS bidirectional neural interface system-on-chip that enables simultaneous recording and stimulation with on-chip stimulus artifact cancelers. The front-end cancellation scheme incorporates a least-mean-square engine that adapts the coefficients of a 2-tap infinite-impulse-response filter to replicate the stimulation artifact waveform and subtract it at the front-end. Measurements demonstrate the efficacy of the canceler in mitigating artifacts up to 700 mVpp and reducing the front-end amplifier saturation recovery time in response to a 2.5 Vpp artifact. Each recording channel houses a pair of adaptive infinite-impulse-response filters, which enable cancellation of the artifacts generated by the simultaneous operation of the 2 on-chip stimulators. The analog front-end consumes 2.5 μW of power per channel, has a maximum gain of 50 dB and a bandwidth of 9.0 kHz with 6.2 μVrms integrated input-referred noise.

SNR on the Four Probe Measurement System at Earth Surface

In the real world, the presence of noise is undeniable. Electric fields, magnetic fields, temperature changes, atomic structures, and so forth are contributing to the reality and the magnitude of noise. Data acquisition of physical quantities in nature is always needed, which subsequently is required for the interpretation in the laboratory. For this reason, the presence of noise needs to be eliminated or known. In the four-probe measurement system, the two electrodes are injecting current, while the other two electrodes are used for acquisition of the arising voltage. The voltage that arises is greatly influenced by the natural environment and the conductor cables, which are usually in long spans and unprotected. For this reason, noise minimization is very needed. This study aims to compare several types of conductors in reducing noise and reducing attenuation. The study was conducted in an open field with a 20-meter cable, and the front-end amplifier was varied to get the highest SNR.

A 0.8V, 152 μW, 433 MHz Mixer-First Receiver with a Self-Adjusted Frequency Tracking Loop

This paper presents a 433 MHz low-power receiver utilizing an N-path filter technique and a self-frequency tracking mechanism. Without the front-end amplifier, the mixer-first architecture can reduce power consumption significantly. A self-adjusted frequency tracking loop (SA-FTL) adjusts local oscillator (LO) frequency to approach input RF frequency automatically, thereby enhancing conversion gain and lowering return loss. The receiver, implemented in a 0.18 μm CMOS process, achieves a sensitivity of -80 dBm at a bit error rate (BER) of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> and a data rate of 10 kb/s, while consuming 152 μW from a 0.8V voltage supply.

Terahertz Integrated Circuits and Systems for High-Speed Wireless Communications: Challenges and Design Perspectives

This paper presents challenges and design perspectives for terahertz (THz) integrated circuits and systems. THz means different things to different people. From International Telecommunication Union (ITU) perspective, THz radiation primarily means frequency range from 300 – 3000 GHz. However, recently, a more expansive definition of THz has emerged that covers frequencies from 100 GHz to 10 THz, which includes sub-THz (100 – 300 GHz), ITU-defined THz frequencies. This definition is now commonly used by communication theorists, and since this paper is intended for people with a wide variety of expertise in system and circuit design, we have adopted the latter definition. The paper brings to the open unmitigated shortcomings of conventional transceiver architectures for multi gigabit-per-second wireless applications, unfolds challenges in designing THz transceivers, and provides pathways to address these impediments. Furthermore, it goes through design challenges and candidate solutions for key circuit blocks of a transceiver including front-end amplifiers, local oscillator (LO) circuit and LO distribution network, and antennas intended for frequencies above 100 GHz.

Analysis and Design of a Broadband Output Stage With Current-Reuse and a Low Insertion-Loss Bypass Mode for CMOS RF Front-End LNAs

This article presents a comprehensive analysis of a novel broadband output stage for external RF front-end low-noise amplifiers (eLNAs). Both variants of the output stage are manufactured using a 130nm bulk CMOS technology. They utilize a common-drain output stage with current-reuse topology, switchable resistive feedback, and source-degeneration. Also, a novel inductor-less low insertion-loss bypass mode is implemented for enhanced bypass functionality. The LNAs are implemented with 4 gain modes achieving excellent RF performance in all possible mobile communication scenarios. Furthermore, an auxiliary linearization circuitry (NMOS IMD sinker) is implemented for variant β to improve linearity performance in low gain mode. Besides, the LNAs support all frequency bands between 1.4GHz and 2.7GHz by only changing the external matching component, allowing easy adaption to different frequency bands. Two offered solutions are realized with a die size of only 0.16mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 0.11mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , respectively. The power consumption is 6.0mW in high gain, 3.6mW in low gain and active-bypass and 0.12mW in bypass mode using a supply voltage of 1.2V. Moreover, a 5.15GHz LNA with high-Q on-chip matching and the broadband output stage is realized and manufactured using a 60nm RF SOI technology. A NF performance of only 1.15dB is achieved consuming only 6.0mW power.

Radio telescope total power mode: improving observation efficiency

Aims. Radio observing efficiency can be improved by calibrating and reducing the observations in total power mode rather than in frequency, beam, or position-switching modes. Methods. We selected a sample of spectra obtained from the Institut de Radio-Astronomie Millimétrique (IRAM) 30-m telescope and the Green Bank Telescope (GBT) to test the feasibility of the method. Given that modern front-end amplifiers for the GBT and direct Local Oscillator injection for the 30 m telescope provide smooth pass bands that are a few tens of megahertz in width, the spectra from standard observations can be cleaned (baseline removal) separately and then co-added directly when the lines are narrow enough (a few km s−1), instead of performing the traditional ON minus OFF data reduction. This technique works for frequency-switched observations as well as for position- and beam-switched observations when the ON and OFF data are saved separately. Results. The method works best when the lines are narrow enough and not too numerous so that a secure baseline removal can be achieved. A signal-to-noise ratio improvement of a factor of √2 is found in most cases, consistent with theoretical expectations. Conclusions. By keeping the traditional observing mode, the fallback solution of the standard reduction technique is still available in cases of suboptimal baseline behavior, sky instability, or wide lines, and to confirm the line intensities. These techniques of total-power-mode reduction can be applied to any radio telescope with stable baselines as long as they record and deliver the ONs and OFFs separately, as is the case for the GBT.

A Low-Noise Chopper Amplifier with Offset and Low-Frequency Noise Compensation DC Servo Loop

The low-frequency and low-amplitude characteristics of neural signals poses challenges to neural signals recording. A low noise amplifier (LNA) plays an important role in the recording front-end. A chopper-stabilized analog front-end amplifier (FEA) for neural signal acquisition is presented in this paper. It solves the noise and offset interference caused by the servo loop in the chopper amplifier structure. The proposed FEA employs a switched-capacitor (SC) integrator with offset and low-frequency noise compensation. Moreover, a dc-blocking impedance is placed for ripple-rejection (RR), and a positive feedback loop is employed to increase input impedance. The proposed circuit is design in a 0.18-µm 1.8-V CMOS process. It achieves a bandwidth of up to 9 kHz for local field potential and action potential signals acquisition. The referred-to-input (RTI) noise is 0.72 µVrms in the 1 Hz~200 Hz frequency band and 3.46 µVrms in the 200 Hz~5 kHz frequency band. The noise effect factor is 0.43 (1 Hz~200 Hz) and 2.08 (200 Hz~5 kHz). CMRR higher than 87 dB and PSRR higher than 85 dB are achieved in the entire pass-band. It consumes a power of 3.96 µW/channel and occupies an area of 0.244 mm2/channel.

Random offset minimization in low frequency front-end amplifiers using swarm intelligence based techniques

Random offset in amplifiers arises mainly due to random variations i.e. inherent mismatch in transistor parameters and greatly impacts its overall design specifications, especially in case of low frequency application. It must be minimized for high precision in the amplifier’s performance. A new approach for minimization of random offset voltage in amplifiers has been proposed through the use of swarm intelligence based optimization algorithms due to their derivative free nature and easy search mechanism. The approach involves firstly, modelling the random offset voltage due to mismatch between transistors parameters based on Pelgrom’s model and then minimizing the formulated model subjected to design constraints using swarm intelligence based algorithms. Two case studies are considered, firstly, a high swing Folded Cascode Operational Transconductance Amplifier (OTA) and secondly, a Recycling Folded Cascode (RFC) OTA. Comparative analysis have been performed by recording best, worst and mean data for 2500 function evaluations and also using statistical analysis such as Friedmann’s test and Mann–Whitney’s U test. The results indicate that the Hybrid Whale Particle Swarm Optimization (HWPSO) algorithm outperforms the other state of the art algorithms by giving a minimum random offset voltage of 7.2 mV and 1.452 mV with a mean rank of 1.55 and 1.75 for the 1st and 2nd case studies respectively. Validation of HWPSO results have been done by performing simulations and Monte Carlo Analysis for the two amplifiers in Cadence Virtuoso, which are found to be in close agreement with the algorithmic results.