Abstract
This paper presents challenges and design perspectives for terahertz (THz) integrated circuits and systems. THz means different things to different people. From International Telecommunication Union (ITU) perspective, THz radiation primarily means frequency range from 300 – 3000 GHz. However, recently, a more expansive definition of THz has emerged that covers frequencies from 100 GHz to 10 THz, which includes sub-THz (100 – 300 GHz), ITU-defined THz frequencies. This definition is now commonly used by communication theorists, and since this paper is intended for people with a wide variety of expertise in system and circuit design, we have adopted the latter definition. The paper brings to the open unmitigated shortcomings of conventional transceiver architectures for multi gigabit-per-second wireless applications, unfolds challenges in designing THz transceivers, and provides pathways to address these impediments. Furthermore, it goes through design challenges and candidate solutions for key circuit blocks of a transceiver including front-end amplifiers, local oscillator (LO) circuit and LO distribution network, and antennas intended for frequencies above 100 GHz.
Highlights
T HE EXPANDED definition of terahertz (THz) band from 100 GHz −10 THz has emerged as part of the professional and public consciousness due to emergence of exciting applications including active and passive sensing/imaging as well as forthcoming generations of high data-rate wireless communications [1]
In the area of wireless communications, which is the scope of this article, mobile networks with nomadic distributed base-stations using unmanned aerial vehicles (UAVs) are expected to become progressively more prevalent in the future society as complementary part of ever-evolving wireless networks, connecting billions of people across the globe and an even higher number of immobile/mobile cyber devices scattered in the environment
LOW-POWER DIRECT-RF-(DE)MODULATION TRANSCEIVERS As discussed in Section II-D, research works in ultra-high speed transceivers have not addressed an essential question: what are the power efficient solutions for DAC/ADC and DSP components of integrated transmitter and receiver chipsets that can handle data rates above 50 Gbps? More precisely, in prior work targeting these applications, the entire back-end and mixed-signal processings are carried out by an expensive commercial Arbitrary Waveform Generator (AWG) and a real-time oscilloscope to generate high-power sub-channelized modulated signals off-chip feeding the transmit side, and to equalize/demodulate/synchronize the RF signal followed by extraction of the baseband stream on the receive side
Summary
T HE EXPANDED definition of terahertz (THz) band from 100 GHz −10 THz has emerged as part of the professional and public consciousness due to emergence of exciting applications including active and passive sensing/imaging as well as forthcoming generations of high data-rate wireless communications [1]. One way of conforming with the need for reliable high data-rate connectivity involves the deployment of distributed base stations with massive number of antennas (>100) providing high-speed wireless access to multi co-channel users (Fig. 2). One can argue that designing an integrated ultra-high data-rate (e.g., above 50 Gbps) wireless transceiver would be practically impossible due to excessive amount of power - as high as 10 W - consumed by data converter and baseband units unless totally new architecture-level solutions are explored This power consumption problem will only exacerbate if a multi-antenna architecture rather than a single-element transceiver at 100+ GHz is to be designed. HEYDARI: TERAHERTZ INTEGRATED CIRCUITS AND SYSTEMS FOR HIGH-SPEED WIRELESS COMMUNICATIONS data/user streams, (2) diversity gain to improve reliability of wireless links especially in non line-of-sight (NLOS) scenarios through transmission of copies of the same data stream, (3) antenna gain to combat path loss, integrated wide-band noise, and co-channel interference through breamforming in LOS or directed NLOS scenarios. This paper makes an attempt to study THz transceivers from both system- as well as circuit-level perspectives
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