Fringing Capacitance Research Articles

Uniform radio frequency fields in loop-gap resonators for EPR spectroscopy

At high frequencies, e.g., Q- and W-bands, it is advantageous to make the axial length of loop-gap resonators (LGRs) at least as long as a free-space wavelength. The opposite scaling of capacitance and inductance with LGR length suggests that the length of an LGR can be increased without limit, with the axial radio frequency (rf) field profiles and resonance frequency independent of length. This scaling is accurate for resonator dimensions much less than one free-space wavelength. When the resonator length approaches one-tenth of a free-space wavelength, the rf field uniformity degrades. From one-tenth to one free-space wavelength, computer simulations and experimental measurements show that the axial magnetic field energy density profile is peaked in the center of the LGR, gradually decreases from 25 to 50% at a distance one radius from the end, and rapidly there-after. The nonuniformity is of two types. One type, in the vicinity of one radius of the end, is caused by the flaring of the field as it curves from the central loop to the end region, into the larger return loop(s). The other type, in the central part of the resonator, is caused by impedance mismatch at the ends of the LGR. The LGR may be viewed as a strongly reentrant (ridge) waveguide nearly open at both ends and supporting a standing wave. A transmission line model relates the central nonuniformity to the fringing capacitance and inductance at the ends of the resonator. This nonuniformity can be eliminated in several ways including modifying the ends of the LGR by adding a small metal bridge or a dielectric ring. These uniformity trimming elements increase the fringing capacitance and/or decrease the fringing inductance. With trimmed ends, LGRs can be made many free-space wavelengths long. The maximum resonator length is determined by the proximity in frequency of the fundamental LGR mode to the next highest frequency mode as well as the quality factor. Results of this theory are compared and conformed with finite-element simulations. This theory connects the uniform LGR with the uniform field cavity resonators previously introduced by this laboratory.

Modeling and Analysis of Planar-Gate Electrostatic Capacitance of 1-D FET With Multiple Cylindrical Conducting Channels

This paper presents accurate analytical models to calculate the electrostatic gate capacitance of 1-D field-effect transistors (FETs) with multiple cylindrical conducting channels. Gate capacitance C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gg</sub> is decomposed into three major components: 1) capacitance C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gc</sub> between the gate and the parallel cylindrical conducting channels (the number of channels ges 1) in dual-layer dielectric materials; 2) outer fringe capacitance C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">of</sub> between the gate and the source/drain cylinder conductors; and 3) coupling capacitance C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gtg</sub> between the adjacent gates. A realistic planar-gate structure with high-k gate dielectric material is considered in this paper, including the screening effect of the parallel conductors and different dielectric materials on capacitance. An accuracy of 10% is achieved from the analytic models, compared with the values that were simulated by 3-D numerical field solvers. Using a simple analytical expression for the gate delay that includes the parasitic capacitance and screening of multiple parallel conducting channels, this paper also shows that both increasing the number of channels per gate and reducing the gate height are effective ways to improve device speed.

A compact C–V model for 120 nm AlGaN/GaN HEMT with modified field dependent mobility for high frequency applications

We present a theoretical model of AlGaN/GaN high electron mobility transistor (HEMT) that includes the effect of spontaneous and piezoelectric polarization. Present model also incorporates the effect of mole fraction dependent mobility, saturation velocity and the accurate 2-DEG density in HEMT as a function of gate voltage in subthreshold, linear and saturation regimes. This paper reports a detailed 2-D analysis of capacitance–voltage (C–V) characteristics. The contribution of various capacitances including fringing field capacitance on the performance of the device is also shown. The model further predicts the transconductance, drain conductance and frequency of operation and is in close proximity with the experimental data which confirms the validity of proposed model.

A method for mechanical characterization of capacitive devices at wafer level via detecting the pull-in voltages of two test bridges with different lengths

The paper aims at developing a wafer-level testing method to examine Young's modulus and residual stress of structural materials of capacitive micro-devices by detecting the pull-in voltages of micro test beams made of the materials to be tested. We derive a formula that correlates the Young's modulus, residual stress and pull-in voltage of the micro test beams. The analytical model considers the fringing field capacitance, the distributed characteristics of the micro test beams and the electromechanical coupling effect. By the present method, one can extract Young's modulus and residual stress simultaneously by detecting the pull-in voltages of two test beams of different lengths. Three common structural materials used in micro-devices are demonstrated: mono-crystalline silicon, poly-silicon and aluminum. The extracted Young's moduli and residual stresses agree very well with the experimental measurement. The present method is expected to be applicable to the wafer-level testing in MEMS device manufacture and compatible with the wafer-level testing in IC industry since the test and the pickup signals are both electrical.

Planar type micromachined probe with low uncertainty at low frequencies

In this paper, we proposed a planar type micromachined probe with low uncertainty and showed its feasibility in practical biomedical applications through the in vivo measurements of cancerous tissue xenografted on nude mice. We have succeeded in increasing the fringe capacitance at low frequencies by locating an aperture on the top side of probe. Furthermore, we showed experimental proof of low uncertainty at low frequencies through measurements of known liquid samples below 1 GHz. Measured results using the proposed probe showed superior agreement with the reference values of the Cole-Cole equation in comparison to measurements made using an open-ended coaxial probe. Muscle and tumor tissue samples of mice, as well as 0.9% saline as a liquid sample, were measured using the proposed probe from 1 GHz to 20 GHz, thus demonstrating the feasibility of this method as a practical biomedical application.

Impact of High-$k$ Gate Dielectrics on the Device and Circuit Performance of Nanoscale FinFETs

The impact of high-k gate dielectrics on device short-channel and circuit performance of fin field-effect transistors is studied over a wide range of dielectric permittivities k. It is observed that there is a decrease in the parasitic outer fringe capacitance C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">of</sub> in addition to an increase in the internal fringe capacitance C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">if</sub> with high-k dielectrics, which degrades the short-channel effects significantly. It is shown that fin width scaling is the most suitable approach to recover the degradation in the device performance due to high-k integration. Furthermore, from the circuit perspective, for the 32-nm technology generation, the presence of an optimum k for a given target subthreshold leakage current has been identified by various possible approaches such as fin width scaling, fin-doping adjustment, and gate work function engineering

Analysis of Geometry-Dependent Parasitics in Multifin Double-Gate FinFETs

This paper analyzes the geometry-dependent parasitic components in multifin double-gate fin field-effect transistors (FinFETs). Parasitic fringing capacitance and overlap capacitance are physically modeled as functions of gate geometry parameters using a conformal mapping method. Also, a physical gate resistance model is presented, combined with parasitic capacitive couplings between source/drain fins and gates. The effects of geometrical parameters on FinFET design under different device configurations are thoroughly studied

Compact high-impedance surfaces integrated with rhombic interdigital structure

A novel compact electromagnetic bandgap structure is presented for size reduction. The proposed structure can be considered as an ameliorated high-impedance surface integrated with a rhombic interdigital structure. This structure significantly enlarges the fringe capacitance between neighbouring elements to compress the overall size of the structure. The measured results show that an even more compact structure can be obtained.

An Analytical Fringe Capacitance Model for Interconnects Using Conformal Mapping

An analytical model is proposed to compute the fringe capacitance between two nonoverlapping interconnects in different layers using a conformal mapping technique. With this technique, electric field lines are geometrically approximated to separately model the different capacitive components. These components are finally combined to obtain the equivalent fringe capacitance. Using the aforementioned technique, a model was developed to compute the capacitances of typical interconnect geometries using technology-dependent parameters. The proposed model closely matches with FASTCAP results and significantly reduces the computational complexity and time in calculating the interconnect capacitances

50-nm Self-Aligned and “Standard” T-gate InP pHEMT Comparison: The Influence of Parasitics on Performance at the 50-nm Node

Continued research into the development of III-V high-electron mobility transistors (HEMTs), specifically the minimization of the device gate length, has yielded the fastest performance reported for any three terminal devices to date. In addition, more recent research has begun to focus on reducing the parasitic device elements such as access resistance and gate fringing capacitance, which become crucial for short gate length device performance maximization. Adopting a self-aligned T-gate architecture is one method used to reduce parasitic device access resistance, but at the cost of increasing parasitic gate fringing capacitances. As the device gate length is then reduced, the benefits of the self-aligned gate process come into question, as at these ultrashort-gate dimensions, the magnitude of the static fringing capacitances will have a greater impact on performance. To better understand the influence of these issues on the dc and RF performance of short gate length InP pHEMTs, the authors present a comparison between In0.7Ga0.3As channel 50-nm self-aligned and standard T-gate devices. Figures of merit for these devices include transconductance greater than 1.9 S/mm, drive current in the range 1.4 A/mm, and fT up to 490 GHz. Simulation of the parasitic capacitances associated with the self-aligned gate structure then leads a discussion concerning the realistic benefits of incorporating the self-aligned gate process into a sub-50-nm HEMT system

Analysis of the gate-source/drain capacitance behavior of a narrow-channel FD SOI NMOS device considering the 3-D fringing capacitances using 3-D simulation

This paper reports an analysis of the gate-source/drain capacitance behavior of a narrow-channel fully depleted (FD) silicon-on-insulator (SOI) NMOS device considering the three-dimensional (3-D) fringing capacitances. Based on the 3-D simulation results, when the width of the FD SOI NMOS device is scaled down to 0.05 mum, the inner-sidewall-oxide fringing capacitance (CFIS), due to the fringing electric field at the edge of the mesa-isolated structure of the FD SOI NMOS device biased at VG=0.3 V and VD=1 V, is the second largest contributor to the gate-source capacitance (C GS). Thus, when using nanometer CMOS devices with a channel width smaller than 0.1 mum, CFIS cannot be overlooked for modeling gate-source/drain capacitance (CGS/CGD)

A new grounded lamination gate (GLG) for diminished fringe-capacitance effects in high-/spl kappa/ gate-dielectric MOSFETs

A grounded lamination gate (GLG) structure for high-kappa gate-dielectric MOSFETs is proposed, with grounded metal plates in the spacer oxide region. Two-dimensional device simulations performed on the new structure demonstrate a significant improvement with respect to the threshold voltage roll-off with increasing gate-dielectric constant (due to parasitic internal fringe capacitance), keeping the equivalent oxide thickness same. A simple fabrication procedure for the GLG MOSFET is also presented

Compact modeling of gate sidewall capacitance of DG-MOSFET

Recent studies show that the gate sidewall capacitance of an underlap double gate device plays an important role in the design and optimization of the device. To date, only semiempirical techniques are used to model this important capacitance. In this brief, the authors present an analytical model of the fringe capacitance and find out a geometry dependent quantity which determines the scaling of this capacitance

Modeling and Significance of Fringe Capacitance in Nonclassical CMOS Devices With Gate–Source/Drain Underlap

Parasitic gate–source/drain (G–S/D) fringe capacitance in nonclassical nanoscale CMOS devices, e.g., double-gate (DG) MOSFETs, is shown, using two-dimensional numerical simulations, to be very significant, gate bias-dependent, and substantially reduced by a well-designed G–S/D underlap. Analytical modeling of the outer and inner components of the fringe capacitance is developed and verified by the numerical simulations; a BOX-fringe component is modeled for single-gate fully depleted silicon-on-insulator MOSFETs. With the new modeling implemented in UFDG, our process/physics-based generic compact model for DG MOSFETs, UFDG/Spice3 shows how nanoscale DG CMOS speed is severely affected by the fringe capacitance and how this effect can be moderated by an optimal underlap, which yields a good tradeoff between the parasitic capacitance and the S/D resistance.

Pull-in voltage study of electrostatically actuated fixed-fixed beams using a VLSI on-chip interconnect capacitance model

A highly accurate computationally efficient closed-form model has been developed to determine the pull-in voltage of an electrostatically actuated fixed-fixed beam. The approach includes the electrostatic spring softening effects due to the fringing field capacitances along with the nonlinear spring hardening effects associated with the load-deflection characteristics of a uniformly loaded fixed-fixed beam. Meijs and Fokkema's highly accurate empirical formula for the capacitance of a VLSI on-chip interconnect has been used to determine the spring softening effects due to the fringing field capacitances. The developed model has been verified by comparing the results with published experimentally verified three-dimensional (3-D) finite element analysis (FEA) results and with those from other published representative closed-form models. The developed model can determine the pull-in voltage with a maximum deviation of 1.27% from the FEA results for small deflections and for large deflections (airgap-beam thickness ratio =12), the deviation from the FEA results is 2.0%. A maximum deviation of 0.5% from the FEA results has been observed for extreme fringing field cases (beamwidth-airgap ratio /spl les/0.5). The model's accuracy range is better compared to the other published models.

Impact of geometry-dependent parasitic capacitances on the performance of CNFET circuits

Intrinsic carbon-nanotube field-effect transistors (CNFETs) have been shown to have superior performance over silicon transistors. In this letter, we provide an insight how the parasitic fringe capacitance in state-of-the-art CNFET geometries impacts the overall performance of CNFET circuits. We show that unless the device (gate) width can be significantly reduced, the effective gate capacitance of CNFET will be strongly dominated by the parasitic fringe capacitances, and the superior performance of intrinsic CNFET over silicon MOSFET cannot be achieved in circuit.

Compact modeling of the effects of parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric nanoscale SOI MOSFETs

A compact model for the effect of the parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric silicon-on-insulator MOSFETs is developed. The authors' model includes the effects of the gate-dielectric permittivity, spacer oxide permittivity, spacer width, gate length, and the width of an MOS structure. A simple expression for the parasitic internal fringe capacitance from the bottom edge of the gate electrode is obtained and the charges induced in the source and drain regions due to this capacitance are considered. The authors demonstrate an increase in the surface potential along the channel due to these charges, resulting in a decrease in the threshold voltage with an increase in the gate-dielectric permittivity. The accuracy of the results obtained using the authors' analytical model is verified using two-dimensional device simulations.

Underlap DGMOS for digital-subthreshold operation

Digital circuits operated in the subthreshold region (supply voltage less than the transistor threshold voltage) is suitable for applications requiring ultralow-power and medium frequency of operation. It is also shown that by optimizing the device structure for subthreshold operation, power dissipation can further be reduced. The impact of gate underlap on the effective gate capacitance of double-gate MOS (DGMOS) transistor for digital-subthreshold operation is analyzed in this paper. It shows that with optimum gate underlap, the parasitic fringe capacitances of DGMOS can be significantly reduced resulting in higher performance and lower power consumption. Results on a ring oscillator show that with optimum underlap, 40% improvement in delay can be achieved with 7.3 /spl times/ reduction in power delay product and a 1-bit full-adder circuit can be operated at 1.25 GHz (V/sub dd/=0.2 V) with 6.2 /spl times/ less power than the one with standard (overlap) DGMOS device.

CAD formulas of the capacitance to ground of square‐spiral inductors with one‐ or two‐layer substrate by synthetic asymptote

AbstractThis paper gives simple CAD formulas of the capacitance to ground of square‐spiral inductors on one‐ or two‐layer substrate by synthetic asymptote. From the derived formula, the equivalent capacitor is a fringe capacitor in parallel with an ideal parallel‐plate capacitor. The average error is less than 2%. © 2006 Wiley Periodicals, Inc. Microwave Opt Technol Lett 48: 972–977, 2006; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.21537.

Comparison of multiple-gate MOSFET architectures using Monte Carlo simulation

Multiple-gate SOI MOSFETs with gate length equal to 25 nm are compared using device Monte Carlo simulation. In such architectures, the short channel effects may be controlled with much less stringent body and oxide thickness requirements than in single-gate MOSFET. Our results highlight that planar double-gate MOSFET is a good candidate to obtain high current drive per unit-width and low subthreshold leakage with aggressive delay time. Additionally, this device offers much better ability to high integration density than nonplanar devices as triple-gate or quadruple-gate MOSFETs. However, we show that source–drain regions have to be carefully scaled to optimize the trade off between access resistance and fringe capacitance.