Frequency Tracking Loop Research Articles

Design and Analysis of a V-Band CMOS Sextuple SILVCO Using Transformer and Cascade-Series Coupling With a Frequency-Tracking Loop

Design and Analysis of a <i>V</i>-Band CMOS Sextuple SILVCO Using Transformer and Cascade-Series Coupling With a Frequency-Tracking Loop

4-Cycle-Start-Up Reference-Clock-Less Digital CDR Utilizing TDC-Based Initial Frequency Error Detection with Frequency Tracking Loop

4-Cycle-Start-Up Reference-Clock-Less Digital CDR Utilizing TDC-Based Initial Frequency Error Detection with Frequency Tracking Loop

A 2.5–5.0-GHz Clock Multiplier With 3.2–4.5-mUIrms Jitter and 0.98–1.06 mW/GHz in 65-nm CMOS

We present a two-stage cascaded clock multiplier with roughly constant energy consumption across 2.5-5.0GHz frequency range. The proposed clock multiplier consists of a reconfigurable delay-locked loop and edge combiner in the first stage while generating a 156.25-312.5MHz clock from 39.0625MHz reference clock frequency. An injection-locked clock multiplier with a frequency tracking loop in the second stage implements a 2.5-5.0 GHz output clock. The clock generation architecture is optimized for the clock multiplication ratio in the two stages and overall power consumption. Designed in TSMC 65nm CMOS process and characterized with post-layout simulations, the first-stage clock multiplier achieves an integrated jitter 1.396-0.607ps <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{rms}$ </tex-math></inline-formula> across 156.25-312.5MHz frequency range at 1.15-2.82mW power consumption. The two-stage clock multiplier gives the total output jitter 1.5-0.9ps <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{rms}$ </tex-math></inline-formula> across 2.5-5.0 GHz output frequency with 0.98-1.06mW/GHz power dissipation.

Development of a generator for percussive ultrasonic drills used in asteroid exploration based on impedance characteristics analysis

Percussive ultrasonic drills participate in asteroid exploration missions. Since space environments are complex and working loads vary dramatically, it is necessary to design a drive that better matches the percussive ultrasonic drill to make it achieve high-speed drilling with low power consumption. Impedance characteristics under different load conditions and the load varying in one drilling cycle are investigated based on analyzing the working principle of the percussive ultrasonic drill. An ultrasonic drill driver with automatic scanning resonant frequency and digital phase-locked loop frequency tracking control is designed according to the load characteristics. Series capacitance impedance matching ultrasonic drills is experimentally studied. Vibration amplitude and impedance characteristics of the ultrasonic drill driven by the designed driver are measured to evaluate the frequency tracking ability and the impedance matching. Finally, ultrasonic drilling experiments are conducted in room, low, and high temperature environments to investigate the driving performance. Under room temperature and 5 N drilling pressure, the speed of ultrasonic drilling into soft sandstone is 52 mm/min, and the power consumption is less than 70 W. The experimental results indicate that the designed driver can drive the percussive ultrasonic drill to achieve stable and high-speed drilling with low power consumption and low drilling pressure.

A 1.12–1.91 mW/GHz 2.46–4.92 GHz Cascaded Clock Multiplier in 65 nm CMOS

We present a low-power and low jitter two-stage 2.46&#x2013;4.92-GHz clock multiplier using a 38.4-MHz reference clock. The proposed clock multiplier implements an <inline-formula> <tex-math notation="LaTeX">$8\times $ </tex-math></inline-formula> clock multiplication with a delay-locked loop and an edge combiner (EC) in the first stage. The regulated supply of the voltage-controlled delay line and EC within the delay-locked loop limits the first-stage clock multiplication voltage sensitivity. An in-depth phase noise analysis of the first stage with the proposed phase domain modeling and spur analysis in the EC helps low-power clock multiplier design. The first-stage output injection locks a pseudo-differential ring oscillator embedded in a frequency tracking loop, thereby achieving a <inline-formula> <tex-math notation="LaTeX">$64\times $ </tex-math></inline-formula>&#x2013;<inline-formula> <tex-math notation="LaTeX">$128\times $ </tex-math></inline-formula> clock multiplication in the second stage. In collaboration with the simulated phase noise from sources, a system-level phase noise modeling defines the design specifications of the two stages for minimum output jitter in a given power budget. Fabricated in a 65-nm CMOS process, the first-stage clock multiplier achieves an integrated jitter 761 fs_rms at 307.2 MHz while consuming 2.5 mW. The mismatch and offset-induced systematic jitter is calibrated, giving &#x2212;53.4-dBc reference spur at the first-stage output. The second-stage injection-locked clock multiplier adds low random jitter to the first stage with total output jitter 825 fs_rms at 4.92 GHz, &#x2212;28.2-dBc reference spur, and 3-mW power consumption.

A Fractional-N Digital LC-PLL Using Coupled Frequency Doubler With Frequency-Tracking Loop for Wireline Applications

This article presents a 23.9–29.4 GHz digital <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LC</i> -phase-locked loop (PLL) architecture with a low phase noise (PN) and power-efficient coupled frequency doubler for 224 Gb/s PAM-4 transmitter clocking. The proposed frequency doubler is designed with two oscillators running at 14 and 28 GHz which are coupled by a transformer. Compared to a conventional frequency doubler or a two-way coupled oscillator, the coupling between the 14 and 28 GHz oscillators provides extra PN reduction as the 14 GHz oscillator can achieve lower PN than the 28 GHz one. In addition, by stacking the two oscillators through the transformer, the current is reused and hence power consumption is reduced. To optimize the PN performance across process, voltage, and temperature (PVT), a compact and power-efficient frequency-tracking loop (FTL) is implemented. The 14 GHz oscillator output is fed to the PLL feedback divider rather than the doubled output, which enables power saving in the prescaler divider in the feedback path. The proposed PLL is fabricated in 10 nm FinFET technology and the PLL achieves a 65 fs random jitter at the transmitter output after a 1st-order 4 MHz-BW CDR filtering which enables the industry’s first 224 Gb/s PAM-4 transmitter. Compared with a reference NMOS-GM <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LC</i> -digitally controlled oscillator (DCO) implemented on the same die, the proposed coupled frequency doubler achieves 4.75 dB lower PN with only a 25% power consumption increase. The <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LC</i> -PLL consumes 17.1 mW from a 0.8/1.0 V regulated supply and occupies an area of 0.088 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Investigation of injection‐locked ring oscillators for process, voltage, and temperature‐aware low phase‐noise reference clock generation

In this paper, injection-locked coupled ring oscillators (ROs) are studied regarding their capabilities for process, voltage, and temperature (PVT) compensated reference clock generation. A PVT resilient RO is implemented by means of injection-locked coupled ROs where the injection locking mechanism is realized by employing adjustable coupling factors. It is shown that the oscillation frequency can be highly compensated for temperature-related variations through the coupling factors. In addition, it is possible to compensate the center oscillation frequency for process-induced variations and supply voltage fluctuations. The proposed technique is fully open loop without any frequency tracking loop and can be easily adopted by other architectures of oscillators such as RC and LC counterparts. A 2.4 GHz reference clock generator is implemented in a 0.18 μm standard CMOS process. While the temperature coefficient (TC) of the free-running ROs is about 640 ppm/°C, the coupled structure offers a TC of 80 ppm/°C. Furthermore, the phase-noise of the coupled structure is about 4 dB lower compared with the free-running ROs. The proposed RO consumes about 2.8 mW and occupies a silicon area of 0.09 mm2.

A Low-Jitter and Low-Spur Charge-Sampling PLL

This article presents a low-jitter and low-spur charge-sampling phase-locked loop (CSPLL). A charge-domain sub-sampling phase detector is introduced to achieve a high phase-detection gain and to reduce the PLL in-band phase noise. Even without employing any power-hungry isolation buffers, the proposed phase detector dramatically suppresses the reference spurs by both minimizing the modulated capacitance seen by the voltage-controlled oscillator (VCO) tank and by reducing the duty cycle of the sampling clock. A 50- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> RF-dividerless frequency-tracking loop is also introduced to lock the CSPLL robustly when the VCO faces a sudden frequency disturbance. Fabricated in a 40-nm CMOS process, the prototype CSPLL occupies a core area of 0.13 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and synthesizes 9.6-to-12-GHz tones using a 100-MHz reference. At 11.2 GHz, it achieves a reference spur of −77.3 dBc and an RMS jitter of 48.6 fs while consuming 5 mW.

A 2.0–2.9 GHz ring-based injection-locked clock multiplier using a self-alignment frequency-tracking loop for reference spur reduction

This paper presents an injection-locked clock multiplier (ILCM) with a digital self-alignment frequency tracking loop (SA-FTL) to reduce the reference spur by calibrating the frequency mismatch and delay offset. To improve the power efficiency, the SA-FTL detects errors in low frequency, where the high-frequency edges from the oscillator are captured by a double-edge snapshot block. The proposed ILCM is fabricated in a 65 nm CMOS process. It has an active area of 0.045 mm2 and consumes 3.1 mW power at 2.5 GHz output. The measured reference spur is -55.6 dB, showing a 15.9 dB improvement with the proposed SA-FTL.

The invention relates to an intermediate frequency power supply fast start and digital phase locked loop control technology

Intermediate frequency induction heating is widely used because of its low energy consumption and high thermal efficiency, but the speed of traditional intermediate frequency power supply is slow and its frequency tracking accuracy is limited. In order to maintain the resonant state of the load during the working process of the induction heating power supply and realize the automatic frequency tracking control during the working process. The frequency tracking of the 40kW intermediate frequency power supply is researched, and a method of combining the resonant frequency automatic identification algorithm and the digital phase locked loop frequency tracking control method is proposed. MATLAB simulation and experiment show that the system based on this control method can save the time of searching the load resonance frequency in the initial stage of the power supply, improve the frequency tracking speed, accelerate the dynamic response speed of the system, avoid the failure of frequency lock, and play the role of fast and stable startup.

A method to improve tracking ability of drive control of MEMS gyroscopes

PurposeA high-precision gyroscope is an important tool for accurate positioning, and the amplitude stability and frequency tracking ability of the drive control system are important and necessary conditions to ensure the precision of micro-electro-mechanical systems (MEMS) gyroscopes. To improve the precision of MEMS gyroscopes, this paper proposes a method to improve the amplitude stability and frequency tracking ability of a drive control system.Design/methodology/approachA frequency tracking loop and an amplitude control loop are proposed to improve the frequency tracking ability and amplitude stability of the drive control system for a MEMS gyroscopes. The frequency tracking loop mainly includes a phase detector, a frequency detector and a loop filter. And, the amplitude control loop mainly includes an amplitude detector, a low-pass filter and an amplitude control module. The simulation studies on the frequency tracking loop, amplitude control loop and drive control system composed of these two loops are implemented. The corresponding digital drive control algorithm is realized by the Verilog hardware description language, which is downloaded to the application-specific integrated circuits (ASIC) platform to verify the performances of the proposed method.FindingsThe simulation experiments in Matlab/Simulink and tests on the ASIC platform verify that the designed drive control system can keep the amplitude stable and track the driving frequency in real time with high precision.Originality/valueThis study shows a way to design and realize a drive control system for MEMS gyroscopes to improve their tracking ability. It is helpful for improving the precision of MEMS gyroscopes.

A 0.8V, 152 μW, 433 MHz Mixer-First Receiver with a Self-Adjusted Frequency Tracking Loop

This paper presents a 433 MHz low-power receiver utilizing an N-path filter technique and a self-frequency tracking mechanism. Without the front-end amplifier, the mixer-first architecture can reduce power consumption significantly. A self-adjusted frequency tracking loop (SA-FTL) adjusts local oscillator (LO) frequency to approach input RF frequency automatically, thereby enhancing conversion gain and lowering return loss. The receiver, implemented in a 0.18 μm CMOS process, achieves a sensitivity of -80 dBm at a bit error rate (BER) of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> and a data rate of 10 kb/s, while consuming 152 μW from a 0.8V voltage supply.

An Ultra-Low-Power 2.4 GHz All-Digital Phase-Locked Loop With Injection-Locked Frequency Multiplier and Continuous Frequency Tracking

This paper presents a 0.46 mW and 2.4 GHz; All-Digital Phase-Locked Loop (ADPLL) through an Injection-Locked Frequency Multiplier (ILFM) and Continuous Frequency Tracking Loop (CFTL) circuitry for low power Internet-of-Thing (IoT) applications. In the proposed ADPLL architecture to save power, the need for Time-to-Digital Converter (TDC) is eliminated through providing the CFTL circuitry. This feature makes the design compact, low power, and suitable for IoT applications. The proposed design is based on a synthesizable pulse injection and frequency-locked loop along with an ultra-low-power LC Digitally-Controlled Oscillator (LC-DCO). The presented CFTL circuit adjusts the frequency of the DCO continuously and prevents the frequency drift after the reference injection. Inside the designed LC-DCO core, the power consumption is minimized by optimizing the $\text{g}_{\mathrm {m}}~/\text{I}_{\mathrm {D}}$ and adjusting the power supply to 0.5 V. The proposed ILFM based ADPLL is fabricated in 55 nm CMOS technology and covers the operational frequency range of 2.402 GHz to 2.480 GHz with a reference frequency of 32 MHz. The measured phase noise performance of the ADPLL is −111.15 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 2.4 GHz. It consumes only 0.46 mW power with an active area of 0.129 mm2.

Towards an Ultra Sensitive Hybrid Mass Sensor Based on Mode Localization without Resonance Tracking.

We present a mode localized mass sensor prototype based on a hybrid system excited at a fixed frequency slightly below the resonances. Indeed, we show, both theoretically and experimentally, that this condition yields higher sensitivities and similar sensitivity ranges than that of resonance peak tracking while being less time consuming than a classical open-loop configuration due to the absence of frequency sweep. The system is made of a quartz resonator and a hardware that includes a resonator and the coupling. The digital aspect allows maximum sensitivity to be achieved with a fine tuning of the different parameters and the implementation of a coupling, regardless of the physical resonator geometry. This allows the generation of mode localization on shear waves resonant structures such as the quartz cristal microbalance widely used in biosensing. This solution has been successfully implemented using resin micro balls depositions. The sensitivities reach almost their maximum theoretical values which means this fixed frequency method has the potential to reach lower limit of detection than the open loop frequency tracking method.

Resonant frequency tracking mode on eddy current pulsed thermography non-destructive testing

Eddy current pulsed thermography (ECPT) has been widely used in the field of non-destructive testing due to its safety, non-contact detection, high spatial resolution and intuitive results. Inductive excitation source is an important component of ECPT and provides high-frequency alternating current to drive the excitation coil. However, a resonant frequency distortion phenomenon exists in the excitation source during the detection process, which seriously affects the output power of the excitation source and the sample detection effect. This paper presents a fast resonant frequency tracking loop for full bridge series resonant inverter which is used to search the resonance frequency in real time through direct digital synthesizer (DDS) and all-digital phase-locked loop. Theoretical analysis and simulation are presented to explain the working principle of the loop. Then, an experimental prototype is manufactured which serves as an excitation source for the ECPT experimental system. Compared with traditional excitation sources, the prototype does not need a water-cooled device and the tracking speed can be adjusted by modifying the parameters of DDS. Finally, experiments have been conducted on both artificial slot of 45# steel and natural cracks of rail and stainless steel to investigate the influence of resonant frequency tracking speed on the crack detection. The results revealed that reducing the resonant frequency tracking time can efficiently improve defect detectability and the manufactured prototype showed more application potential. This article is part of the theme issue 'Advanced electromagnetic non-destructive evaluation and smart monitoring'.

3.125-to-28.125 Gb/s 4.72 mW/Gb/s Multi- Standard Parallel Transceiver Supporting Channel-Independent Operation in 40-nm CMOS

This paper presents a 3.125-to-28.125 Gb/s dual-lane multi-standard parallel transceiver supporting channel-independent operation. Network equipment supports multiple data rates to encompass diversified communication standards. However, network equipment supports only a fixed number of channels at each supported data rate. This lack of flexibility limits the utilization rate of the network equipment. This study proposes a clock and data recovery (CDR) IC to obtain utilization flexibility and scalability in each channel with complete channel independency. The CDR IC achieves a wide tuning capability for data rates ranging from 3.125 to 28.125 Gb/s with low clock jitter owing to the use of injection-locked oscillators in each channel. Each CDR lane generates a channel-independent injection clock signal with a fixed-frequency global clock signal using a variable clock divider and a phase rotator with the proposed harmonic distortion compensator. In addition, a frequency tracking loop is proposed using a bang-bang phase detector-based natural frequency detector to align the natural frequency of the injection-locked oscillator with the input data rate, thereby suppressing the injection spur. The test chip fabricated in a 40 nm CMOS exhibits a power efficiency of 4.72 mW/Gb/s, while generating a recovered clock jitter of 976 fsrms at a data rate of 25.78125 Gb/s.

Phase-domain ADC with ∆-modulation frequency tracking loop

The principle of ∆-modulation has been leveraged in time-domain to cancel the nonlinearity of voltage to frequency transfer function in VCO-based ADCs. The proposed modulation technique features frequency-tracking loop (FTL) to compensate for the imperfection of frequency nonlinearities and to eliminate the analog Op-Amp. Injection locking is used to alleviate the mismatch effect between the feedforward and feedback paths. The circuit level design and simulation results validate the functionality. The proposed solution can achieve higher noise shaping orders and better resolutions without compromising the hardware complexity by using fully synthesizable digital accumulators.

A Fully Integrated 0.27-THz Injection-Locked Frequency Synthesizer With Frequency-Tracking Loop in 65-nm CMOS

A fully integrated sub-terahertz (sub-THz) frequency synthesizer is proposed cascading a radio frequency subsampling phase-locked loop (SS-PLL) with millimeter-wave injection-locked frequency multipliers (ILFMs) and a sub-THz mixer for frequency extension. Enhanced third-harmonic and fourth-harmonic-extraction techniques are proposed for the ILFMs with different multiplication ratios. In addition, a frequency-tracking loop (FTL) with automatic frequency and amplitude calibration is embedded for the ILFMs. Finally, a distributed bias technique is employed to improve the linearity of the wideband magnetic-tuning sub-THz oscillator. Designed in a 65-nm CMOS process, the proposed prototype achieves an ultra-wide frequency tuning range from 61.2 to 100.8, 122.4 to 136.8, and 198.5 to 273.6 GHz with a phase noise at 1-MHz offset from -79.3 to -95.4 dBc/Hz and an integrated jitter from 124 to 159 fs over the tuning range. The synthesizer occupies a core area of 0.58 mm2 and measures an output power of -11 dBm at 211.4 GHz with 49.5 mW, corresponding to a dc-to-radio frequency (RF) efficiency of 0.16%, an FoM from -171.4 to -177.7 dBc/Hz, and FoMT from -177 to -190.5 dBc/Hz.

An mm-Wave Synthesizer With Robust Locking Reference-Sampling PLL and Wide-Range Injection-Locked VCO

In this article, a two-stage millimeter (mm)-wave frequency synthesizer with low in-band noise and robust locking reference-sampling techniques is presented. Using a two-stage scheme allows separately dealing with the low phase noise (PN) frequency synthesis in the first stage and the mm-wave frequency multiplication in the second stage, achieving the best overall power efficiency. In the first stage, a voltage domain reference-sampling phase detector (RSPD)-locked loop (RSPLL) is adopted to achieve both low PN and robust locking without additional frequency locking loop. A reference reshaping buffer is implemented to improve the phase detector gain and in-band PN. The reference rising/falling time is programmable to achieve optimal RSPLL performance even under external disturbances. The second stage employs an injection-locked voltage-controlled oscillator (ILVCO) for 4 $\times $ frequency multiplication. A low-power digital frequency tracking loop (FTL) detecting actual frequency errors is implemented in order to achieve wide operation range for the ILVCO while using a high ${Q}$ tank with low power. The prototype synthesizer was fabricated in a 45-nm partially depleted silicon on insulator (PDSOI) CMOS technology. The first stage 9-GHz RSPLL achieves 144-fs integrated jitter with 7.2-mW power consumption, achieving a figure of merit (FoM) of −248 dB and the overall mm-wave synthesizer achieves 251-fs integrated jitter with 20.6-mW power consumption at 35.84 GHz, achieving an FoM of −238.9 dB.

Performance assessment of GNSS scalar and vector frequency tracking loops

This paper focuses on two types of frequency lock loops (FLL) in Global Navigation Satellite System (GNSS) receivers, namely the conventional scalar frequency lock loop (SFLL) and the vector frequency lock loop (VFLL).The VFLL has been proven to have a better tracking performance than the SFLL in scenarios such as intermittent signal outages, high dynamics, etc. However, the FLL tracking performance under the equivalent noise bandwidth has not been explored in literature. To do this, we implemented three kinds of FLL, i.e., the SFLL, the weighted least square-based vector frequency loop (WLS-VFLL), and the extended Kalman filter-based vector tracking loop (EKF-VFLL). All these FLLs have the same noise bandwidth, based on which we made a fair comparison between them. The experimental static data and simulated high- dynamic data have been tested. Results show that the EKF-VFLL has a similar tracking performance with WLS-VFLL under static environment, both better than the SFLL. In high- dynamic environment, the advantages of EKF-VFLL are more prominent than the other two methods. Furthermore, EKF-VFLL takes the longest time in terms of computational efficiency.