Frequency Tracking Loop Research Articles

A 2.5–5.75-GHz Ring-Based Injection-Locked Clock Multiplier With Background-Calibrated Reference Frequency Doubler

A low-jitter, low-power ring oscillator (RO)-based injection-locked clock multiplier (ILCM) is presented. It employs a background-calibrated reference frequency doubler to increase the RO noise suppression bandwidth, a digital delay-locked loop (DLL) to achieve second-order suppression of RO noise, and a digital frequency-tracking loop (FTL) to continuously tune the oscillator's free-running frequency and ensure a robust operation across process, voltage, and temperature (PVT) variations. A least-mean-square (LMS) algorithm is used to accurately cancel the deterministic jitter (DJ) caused by input duty cycle errors. Fabricated in the 65-nm CMOS process, the prototype ILCM occupies an active area of 0.09 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and generates an output clock in the range of 2.5-5.75 GHz using a 125-MHz reference clock. At 5 GHz, it achieves an integrated jitter of 335 fsrms, while consuming 5.3 mW of power. This translates to the best reported figure-of-merit (FoM) of -242.4 dB for a ring-based ILCM at this high frequency.

FPGA-Based Automatic Frequency-Controlled Resonant Inverter for Induction Heating System

This paper presents a frequency tracking control for the half-bridge high-frequency series resonant inverter-fed induction heating system. The aim of this research work is to obtain dynamic zero current switching in the switches of the inverter even under variation in the load. Closed loop frequency tracking control system is developed to track the resonant frequency during step change in load. The change in load is identified by sensing the phase angle between voltage and current. The error in the phase angle is used to track the frequency. Simulation of an open loop and closed loop IH systems has been performed. A simulation study is performed to verify the effect of controller. Simulation results of half-bridge series resonant inverter system with the proposed controller are presented to prove the performance of the developed control system. The results are validated with the prototype of system controlled by FPGA controller.

A 0.0056-mm2 −249-dB-FoM All-Digital MDLL Using a Block-Sharing Offset-Free Frequency-Tracking Loop and Dual Multiplexed-Ring VCOs

This paper describes an ultra-compact all-digital multiplying delay-locked loop (MDLL) featuring a low-power block-sharing offset-free frequency-tracking loop (FTL) to calibrate the process–voltage–temperature variations of the voltage-controlled oscillator (VCO) frequency. Such FTL utilizes a digital-controlled delay line (DCDL)-based low-power time-interval comparator and an adjacent-edge selector, to precisely detect the static phase offset (SPO) caused by the VCO frequency drifting in the presence of reference injection. The block-sharing-based SPO detection aids nullifying the circuit-mismatch- and offset-induced deterministic error. Also, for the adjacent edge selector, block sharing between its control generation circuits and the coarse FTL further reduces the power consumption. The varactor-tuned dual multiplexed-ring VCOs (MRVCOs) serve to reduce jitter variation while extending the frequency tuning range. Fabricated in a 28-nm CMOS with a core area of 0.0056 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , the proposed MDLL covers a tuning range from 1.55 to 3.35 GHz, and exhibits a root-mean-square (rms) jitter of 292 fs at 3-GHz output, under a 200-MHz reference clock. The power consumption is 1.45 mW at a 0.8-V supply, resulting in an FoM of −249 dB favorably comparable with the state of the art.

Frequency tracking loop with wide pull‐in range for weak DSSS signal

A frequency tracking loop based on triangle function frequency discriminator and adaptive loop bandwidth adjustment is proposed to track the Doppler frequency of weak direct-sequence spread spectrum (DSSS) signal. The proposed structure first provides a frequency discrimination with wide pull-in range to lock the large residual frequency offset after acquisition. Then, the adaptive loop bandwidth adjustment is employed to improve the accuracy of frequency estimation. Compared with the conventional tracking loop, the proposed structure has wider pull-in range and higher sensitivity. Simulation results verify the validity of the proposed method.

A 6.75–8.25-GHz −250-dB FoM Rapid ON/OFF Fractional-N Injection-Locked Clock Multiplier

A rapid ON/OFF LC-based fractional-N injection-locked clock multiplier (ILCM) is presented. The proposed architecture extends the merits of ILCMs to fractional-N operation. It employs a high-resolution digital-to-time converter to align the injected pulses to the oscillator’s zero crossings. An all-digital frequency-tracking loop continuously tunes the oscillator free-running frequency toward the target output frequency. The proposed clock multiplier can be powered ON from a completely OFF state almost instantaneously. Background calibration techniques ensure that robust operation across process, voltage, and temperature. Fabricated in 65-nm CMOS process with an active area of 0.27 mm2, the prototype ILCM generates output clock in the range of 6.75–8.25 GHz using a 115-MHz reference clock. It achieves integrated jitter performance of 109 fsrms (integer-N) and 177 fsrms (fractional-N), while consuming only 2.65 (integer-N) and 3.25 mW (fractional-N). This translates to the best-reported FoMJ of −255 (integer-N) and −250 dB (fractional-N). The turn-on time is less than 4 ns in both the integer- and fractional-N modes, illustrating almost instantaneous settling.

An Injection Frequency-Locked Loop—Autonomous Injection Frequency Tracking Loop With Phase Noise Self-Calibration for Power-Efficient mm-Wave Signal Sources

This paper presents a fast and autonomous injection frequency tracking and locking technique. In the present injection-locking system, a quadrature injection-locked oscillator (QILO) is third harmonically locked to a quadrature voltage-controlled oscillator (QVCO). In the frequency tracking loop, the frequency difference between QVCO and QILO is extracted using the QILO’s amplitude modulated (AM) envelope waveform. The AM frequency of the envelope signal bears frequency difference between the two oscillators. The envelope signal is further converted to pulse signal which subsequently drives digital feedback control circuitry to update the QILO’s output frequency so that it can track the third harmonic of the injection QVCO. The frequency calibration process is purely autonomous, self-initiating whenever the AM modulated envelope waveform is generated. The feedback signal is primarily processed in the digital domain, resulting in a compact, fast, and power-efficient injection frequency-locked loop (IFLL). By incorporating a phase noise (PN) calibration routine after completing the frequency calibration, the presented IFLL resolves the intractable issue of PN degradation at the edge of the slave oscillator’s injection locking range. This results in a large injection frequency tracking range of 26.5–29.7 GHz which is only limited by the QILO’s LC tank tuning range. The IFLL realized in 0.13- $\mu \text{m}$ CMOS consumes 2.4 mW with a negligible area penalty. Overall chip size including QVCO, QILO, and IFLL is $1 \times 1$ mm2.

A Low-Integrated-Phase-Noise 27–30-GHz Injection-Locked Frequency Multiplier With an Ultra-Low-Power Frequency-Tracking Loop for mm-Wave-Band 5G Transceivers

An ultra-low-phase-noise injection-locked frequency multiplier (ILFM) for millimeter wave (mm-wave) fifth-generation transceivers is presented. Using an ultra-low-power frequency-tracking loop (FTL), the proposed ILFM is able to correct the frequency drifts of the quadrature voltage-controlled oscillator of the ILFM in a real-time fashion. Since the FTL is monitoring the averages of phase deviations rather than detecting or sampling the instantaneous values, it requires only 600 $\mu \text{W}$ to continue to calibrate the ILFM that generates an mm-wave signal with an output frequency from 27 to 30 GHz. The proposed ILFM was fabricated in a 65-nm CMOS process. The 10-MHz phase noise of the 29.25-GHz output signal was −129.7 dBc/Hz, and its variations across temperatures and supply voltages were less than 2 dB. The integrated phase noise from 1 kHz to 100 MHz and the rms jitter were −39.1 dBc and 86 fs, respectively.

A Cyclic Frequency Tracking Loop for Wideband Spectrum Sensing and FM Demodulation

A cyclostationary feature-based wideband spectrum sensing is proposed in which cyclic frequency offset is considered. The received signal passes through a rough and flexible filter which its effective band tuned to a specific part of the received signal spectrum. It belongs to a target signal, which possibly exists in the received signal. Some cyclic frequencies of the target are employed to derive the normalized least mean square algorithm that estimates the filter output from its frequency shifted samples. Based on the weight estimate’s norm, the algorithm is tuned to find the accurate cyclic frequencies. If it succeeded, it means that the target signal is present. On the other hand, a complete search without major weights estimate means that the target signal is absent. In addition, the overall system, named cyclic frequency lock loop can be reformed as a demodulator for sinusoidal frequency modulation signals. The method is very easy to implement and has less computational complexity comparing with its other spectrum sensing counterparts. Simulation results validate the efficiency of the proposed method.

A PVT-Robust and Low-Jitter Ring-VCO-Based Injection-Locked Clock Multiplier With a Continuous Frequency-Tracking Loop Using a Replica-Delay Cell and a Dual-Edge Phase Detector

A low-jitter, ring-type voltage-controlled oscillator (VCO)-based injection-locked clock multiplier (ILCM) with a continuous frequency-tracking loop (FTL) for process-voltage-temperature (PVT)-calibration is presented. Using a single replica-delay cell of the VCO that provides the intrinsic phase information of the free-running VCO, the proposed FTL can continuously track and correct frequency drifts. Therefore, the proposed ILCM can calibrate real-time frequency drifts due to voltage or temperature variations as well as static frequency deviations due to process variations. Since the FTL provided an additional filtering of in-band VCO noise, the ILCM was able to achieve excellent jitter performance over the PVT variations, while it was based on a ring-VCO. The proposed ILCM was fabricated in a 65 nm CMOS process. When injection locked, the RMS-jitter integrated from 10 kHz to 40 MHz of the 1.20 GHz output signal was 185 fs. The proposed PVT-calibrator regulated the degradations of jitter to less than 5% and 7% over temperatures and supply voltages, respectively. The active area was $\text {0.06 mm}^{2}$ and total power consumption was 9.5 mW.

Design and Analysis of Low-Power High-Frequency Robust Sub-Harmonic Injection-Locked Clock Multipliers

A low-jitter, low-power LC-based injection-locked clock multiplier (ILCM) with a digital frequency-tracking loop (FTL) is presented. Based on a pulse gating technique, the proposed FTL continuously tunes the oscillator’s free-running frequency to ensure robust operation across PVT variations. The FTL resolves the race condition existing in injection-locked PLLs by decoupling frequency tuning from the injection path, such that the phase-locking condition is only determined by the injection path. This paper also introduces an accurate theoretical large-signal analysis for phase domain response (PDR) of injection-locked oscillators (ILOs). The proposed PDR analysis captures the asymmetric nature of ILO’s lock-in range, and the impact of frequency error on injection strength and phase noise performance. The proposed architecture and analysis are demonstrated by a prototype fabricated in 65 nm CMOS process with active area of $0.25\;\text{mm}^2$ . The prototype ILCM generates output clock in the range of 6.75–8.25 GHz by multiplying the reference clock by 64. It achieves superior integrated jitter performance of $190\;\text{fs}_{\text{rms}}$ , while consuming 2.25 mW power. This translates to an excellent figure-of-merit (FoM) of $-251\;\text{dB}$ , which is the best reported high-frequency clock multiplier.

Automated high-throughput viscosity and density sensor using nanomechanical resonators

Most methods used to determine the viscosity and mass density of liquids have two major drawbacks: relatively high sample consumption (∼milliliters) and long measurement time (∼minutes). Resonant nanomechanical cantilevers promise to overcome these limitations. Although sample consumption has already been significantly reduced, the time resolution was rarely addressed to date. We present a method to decrease the time and user interaction required for such measurements. It features (i) a droplet-generating automatic sampler using fluorinated oil to separate microliter sample plugs, (ii) a PDMS-based microfluidic measurement cell containing the resonant microcantilever sensors driven by photothermal excitation, (iii) dual phase-locked loop frequency tracking of a higher-mode resonance to achieve millisecond time resolution, and (iv) signal processing to extract the resonance parameters, namely the eigenfrequency and quality factor. The principle was validated by screening series of 3μL droplets of glycerol solutions separated by fluorinated oil at a rate of ∼6s per sample. An analytical hydrodynamic model (Van Eysden and Sader, 2007 [6]) and a reduced order model (Heinisch et al., 2014 [16]) were employed to calculate the viscosity and mass density of the sample liquids in a viscosity range of 1–10.5mPas and a density range of 998–1154kgm−3.

Research on the Compound Frequency Tracking Mode of Ultrasonic Power Based on DSP

Aiming at the problem that the tracking frequency range of ultrasonic power is fixed, and the accuracy of tacking frequency is low, the tactics of digital phase-locked loop frequency tracking technology combined with changing step searching circuit peak is proposed. The frequency tracking is achieved by combining the advantages of digital phase-locked loop frequency tracking technology with changing step searching circuit peak, building the digital phase detector circuit and current effective value converter circuit, taking the feedback of sampling the phase and circuit peak as basic of frequency tracking. Build the simulating model in Multisim. The experiment results show that composite frequency tracking strategy can effectively achieve frequency tracking and dynamically lock transducer multi-modal resonance.

A Transducer Matching Method with Signal Frequency and Inductor Adjustment Combined for Submerged Structure Ultrasonic Cleaning

The application of ultrasonic cleaning for submerged structure is more common, but the resonant frequency of piezoelectric transducer is changed when it is heat at work. The traditional matching method cannot adapt the serial resonance frequency of capacitance branch and dynamic tuning is inefficient. We proposed a transducer matching method with signal frequency and inductor adjustment combined. The technique of identifying true max current value and Phase Locked Loop frequency tracking was used. The automatic tracing of frequency is realized by searching the max current value, and working current was exceeding the threshold of 0.9Imax. The adjustment of inductor was decided by phase comparison and impedance matching was achieved finally. By combining experimental study with theoretical analysis, the feasibility of this dynamic matching method was verified.This method have important significance for improving submerged structure ultrasonic cleaning efficiency.

The Application of Phase-Locked Loop Frequency Tracking in the Intelligence-Type Induction Heating Power Supply

As the induction heating power was working, its load resonant frequency constantly changes. In order to improve the efficiency of power supply, it requires that the inverter output frequency can follow changes in natural frequency of the load, namely the frequency tracking control. Aiming at the deficiency of the frequency tracking control system, this paper presents a method that the phase locked loop (PLL) tracking system works on real-time control of the output frequency of the power supply,and introduces a phase locked mathematical model which fits the inverter power supply, and offers a simulated analysis by using PSPICE. Through experiments, the system proves to be good at frequency tracking.

Design of Frequency Tracking Loop for Satellite-Based AIS

Due to a wide range of Doppler frequency shift and low SNR existing in the AIS transmission, it is difficult to decode correctly in Satellite-based AIS receiver. In order to solve the problem, a new design of PLL is proposed based on the theory of conventional PLL. The new design is aided by ML estimating. In the algorithm, frequency offsets are reduced to the fast capture zone after compensations to received AIS signals and then the phase locked loop start to track surplus frequency offsets. The simulation results indicate that the algorithm requiring the symbol number of fast capture is less than 256(the number of AIS frame symbols) when the SNR is 1dB and tracking precision is within 2 Hz. And it can be used under conditions of low SNR with large frequency offsets.

A phase-locked loop frequency tracking system for portable microelectromechanical piezoresistive cantilever mass sensors

A closed-loop circuit is developed in this work for tracking the resonant frequency of silicon microcantilever mass sensors. The proposed closed-loop system is mainly based on a phase-locked loop (PLL) circuit. To lock onto the resonant frequency of the resonator, an actuation signal generated from a voltage-controlled oscillator is fed back to the input reference signal of the cantilever sensor. In addition to the PLL circuit, an instrumentation amplifier and an active low-pass filter are connected to the system for gaining the cantilever output signal and transforming a rectangular PLL output signal into a sinusoidal signal used for sensor actuation, respectively. To demonstrate the functionality of the system, a self-sensing silicon cantilever resonator with a built-in piezoresistive Wheatstone bridge is fabricated and integrated with the circuit. A piezoactuator is employed to actuate the cantilever into resonance. From the measurement results, the integrated closed-loop system is successfully employed to characterize a 9.4 kHz cantilever sensor under ambient temperature cross-sensitivity yielding a sensor temperature coefficient of −32.8 ppm/°C. In addition to it, the sensor was also exposed to exhaled human breath condensates and e-cigarette aerosols to test the sensor sensitivity obtained from mass-loading effects. With a high frequency stability (i.e., a frequency deviation as low as 0.02 Hz), this developed system is intended to support the miniaturization of the instrumentation modules for cantilever-based nanoparticle detectors (CANTORs).

Tracking Frequency Resonant Coupling Energy Wireless Transmission Research

The problem of transceiver coil resonance frequency detuning is solved tentatively on resonant coupling energy wireless transmission in this paper. The circuit model of the wireless transmission system of the resonant coupling electrical energy is first studied, the relationship between the parameters of the system and the transmission efficiency of the various parts is analyzed, and yhe studies have shown that the change in the amount of the transmitting coil inductance greater impact on the transmission efficiency, while the receiving coil inductance change in the amount of efficiency small, and thus the proposed phase locked loop frequency tracking technology, to ensure that the transceiver coil resonant frequency to ensure that the transmission efficiency of the system. The feasibility of the design frequency tracking system is verified with the experimental results.

Resonance Tracking of Nonlinear MEMS Resonators

In this paper, the frequency control loop performance of nonlinear microelectromechanical resonators is investigated. A phase-locked loop (PLL) controller is used to track the resonance frequency of a nonlinear resonator and to compensate for the changes in the natural frequency. Based on the harmonic balance approach, governing equations of the dynamics of a nonlinear resonator are obtained, and using the mathematical model of the PLL, a new stability criterion for the closed-loop system is proposed. The relationship between the amplitude of the external driving force command and the stability of the control loop is elaborated for both hardening and softening nonlinearities. A nonlinear gain control strategy is proposed for the frequency-tracking loop, and its effectiveness is shown through simulation studies.

A Robust Frequency Tracking Loop for Energy-Efficient Crystalless WBAN Systems

This brief presents a frequency tracking loop (FTL) to realize a crystalless wireless sensor node (WSN) for wireless body area network (WBAN). By tracking a remote wireless RF reference for system clock calibration, the proposed FTL allows WSNs to tolerate a large-frequency error from on-chip CMOS oscillators. Moreover, to achieve energy-efficient transmissions in crystalless, a sufficiently accurate convergence clock is required to enable burst overmegabits-per-second system throughput with minimized operation duty cycle. For the dedicated purpose, a comparison-based binary-search tracking scheme, which ensures accurate and robust convergence against noisy wireless channel, is further developed to manage the operation of FTL. The intermediate frequency back-end part of FTL is implemented in 90-nm CMOS process. Measurement results show that the FTL extends an initial tolerance of system clock error to ±3% and achieves a final quartz-crystal comparable ±50-ppm accuracy. This enables 4.85-Mb/s wireless links and improves 79% energy efficiency by RF operation-time reduction, giving a power-saved and miniaturized WSN device for WBAN applications.

Joint Carrier Synchronization and Equalization Algorithm for Packet-Based OFDM Systems Over the Multipath Fading Channel

In this paper, a joint carrier synchronization and equalization algorithm is presented for orthogonal frequency-division multiplexing (OFDM) systems in the tracking stage. Based on the minimum mean-square-error (MMSE) criterion, the cost function of the joint algorithm is proposed to minimize the mean square error (MSE), namely, the uncoded bit error rate (BER), on each subchannel and to further lower the carrier frequency jitter concurrently. The carrier synchronization scheme with multirate processing is a dual-loop structure, which is composed of outer and inner loops. The outer loop is a frequency-tracking loop that deals with the phase offset, which is induced by the carrier frequency offset (CFO), in the time domain. The inner loop is a phase-tracking loop to cope with the phase distortions, which are caused by the carrier frequency error and the channel phase variation, on each subcarrier in the frequency domain. There is a gain equalization loop to compensate the magnitude distortion on each subchannel. Furthermore, the closed-loop stability of the carrier synchronization loop is particularly explored for the loop delay induced by hardware realization. Many simulations are done for the additive white Gaussian noise (AWGN) and the multipath frequency-selective fading channels to show that the joint algorithm not only accurately estimates and compensates the CFO and the channel impairment but also provides the cost-effective feature compared with the considered algorithms.