Frequency Search Algorithm Research Articles

A frequency and two-hop configuration checking-driven local search algorithm for the minimum weakly connected dominating set problem

A frequency and two-hop configuration checking-driven local search algorithm for the minimum weakly connected dominating set problem

A Mechanism-Based Automatic Fault Diagnosis Method for Gearboxes

Convenient and fast fault diagnosis is the key to improving the service safety and maintenance efficiency of gearboxes. However, the environment and working conditions under complex service conditions are variable, and there is a lack of fault samples in engineering applications. These factors lead to difficulties in intelligent diagnosis methods based on machine learning, while traditional mechanism-based fault diagnosis requires high expertise and long time periods for the manual analysis of data. For the requirements of diagnostic convenience, an automatic fault diagnosis method for gearboxes is proposed in this paper. The method achieves accurate acquisition of rotational speed by constructing a rotational frequency search algorithm. The self-referencing characteristic frequency identification method is proposed to avoid manual signal analysis. On this basis, a framework of anti-interference automatic diagnosis is constructed to realize automatic diagnosis of gear faults. Finally, a gear fault experiment is carried out based on a high-fidelity experimental bench of bogie to verify the effectiveness of the proposed method. The proposed automatic diagnosis method does not rely on a large number of fault samples and avoids the need for diagnosis through professional knowledge, thus saving time for data analysis and promoting the application of fault diagnosis methods.

A 50-V Isolation, 100-MHz, 50-mW Single-Chip Junction Isolated DC-DC Converter With Self-Tuned Maximum Power Transfer Frequency

A fully integrated, point-of-load, low-noise, isolated dc–dc converter for supply regulation of high dynamic range analog and mixed-signal isolated sensor signal-chains is presented. The isolated dc–dc converter utilizes an integrated planar air-core micro-transformer as a coupled-resonator and an isolation barrier, and enables direct connection of low-voltage mixed-signal circuits to higher supply rails for current and voltage sensing. The transformer is driven at its resonant frequency of 100 MHz to achieve maximum power transfer. A mixed-signal perturb-and-observe-based frequency search algorithm is developed to improve maximum power transfer efficiency by 60% across the isolation barrier compared to fixed driving frequency method. The switching ripple at output is reduced by 11 dB utilizing spread spectrum clocking in the driver, and 21 dB using a low-dropout regulator. Conducted and radiated EMI distribution on the IC is measured by a set of proposed ring oscillator-based noise sensors with −68-dBm noise sensitivity. The proposed isolated converter achieves the highest level of integration compared to state-of-the-art integrated isolated converters, and provides 50-V on-chip junction isolation using standard CMOS technology.

Fast Automatic Frequency Calibrator Using an Adaptive Frequency Search Algorithm

A new adaptive frequency search algorithm (A-FSA) is presented for a fast automatic frequency calibrator in wideband phase-locked loops (PLLs). The proposed A-FSA optimizes the number of clock counts for each frequency comparison cycle, depending on the difference between the target frequency and the PLL output frequency, as opposed to a binary frequency search algorithm (B-FSA), where the frequency search time per cycle is fixed. This eliminates unnecessary clocking times during the frequency comparison process, and thus reduces the total PLL lock time. The additional circuitry needed for A-FSA is only a simple counter controller, thus minimizing hardware overhead. To verify the effectiveness of the proposed algorithm, two wideband PLLs are designed and simulated using a 65-nm CMOS technology: one with B-FSA, and the other with A-FSA. The latter achieves a lock time faster than the former by at least a factor of 2, even under worst case conditions.

Multi-format carrier recovery for coherent real-time reception with processing in polar coordinates.

A blind frequency and phase search algorithm for joint frequency and phase recovery is introduced. The algorithm achieves low complexity due to processing in polar coordinates, which reduces the amount of multiplications. We show an implementation for real-time processing at 32 GBd on FPGA hardware. The hardware design allows for dynamic multi-format operation, where the format can be switched flexibly after each clock cycle (250 MHz, 128 Symbols) between 4QAM, 8QAM, and 16QAM. The performance of the algorithm is evaluated with respect to laser phase noise, carrier frequency offset, and carrier frequency offset drift. The effect of working with limited hardware resources is investigated. An FPGA implementation shows the feasibility of our carrier recovery algorithm with a negligible penalty when compared to a floating point simulation.

DFIG-based offshore wind power plant connected to a single VSC-HVDC operated at variable frequency: Energy yield assessment

The existence of HVDC (High Voltage Direct Current) transmission systems for remote offshore wind power plants allows devising novel wind plant concepts, which do not need to be synchronized with the main AC grid. This paper proposes an OWPP (offshore wind power plant) design based on variable speed wind turbines driven by DFIGs (doubly fed induction generators) with reduced power electronic converters connected to a single VSC-HVDC converter which operates at variable frequency and voltage within the collection grid. It is aimed to evaluate the influence of the power converter size and wind speed variability within the WPP on energy yield efficiency, as well as to develop a coordinated control between the VSC-HVDC converter and the individual back-to-back reduced power converters of each DFIG-based wind turbine in order to provide control capability for the wind power plant at a reduced cost. To maximise wind power generation by the OWPP, an optimum electrical frequency search algorithm for the VSC-HVDC converter is proposed. Both central wind power plant control level and local wind turbine control level are presented and the performance of the system is validated by means of simulations using MATLAB/Simulink®.

A Fast Locking Digitally Controlled PLL for Constant-Gain Digitally Controlled Oscillator

A fast locking digitally controlled phase-locked loop (DCPLL) with a novel frequency search algorithm is presented in this paper. The proposed frequency search algorithm can predict the target code by two predetermined codes and the two corresponding digital phase errors. To implement the proposed frequency algorithm in the PLL, a DCPLL with a constant-gain digitally controlled oscillator is developed and implemented in SMIC 0.13m 1P8M technology. Finally, the frequency acquisitions are simulated for the whole frequency range. The simulation results show that the maximum locking time of the DCPLL is four reference clock cycles.

An All-Digital Large-$N$ Audio Frequency Synthesizer for HDMI Applications

In this brief, a novel all-digital and large-frequency-multiplication-ratio audio frequency synthesizer for high-definition multimedia interface applications is presented. The proposed large- N frequency synthesizer is designed in an all-digital manner to reduce circuit complexity and design efforts in advanced CMOS process technology, as compared with prior studies. The proposed frequency synthesizer does not require an extra high-frequency reference clock source but employs a single locking loop to reduce lock-in time and enhance loop stability. Based on the proposed frequency search algorithm and the high-resolution digitally controlled oscillator, the frequency synthesizer cannot only provide a large frequency multiplication ratio, but it also achieves low-jitter performance. Measurement results show that the frequency multiplication ratio has a range of 4096 to 25 088 and that the power consumption of the proposed frequency synthesizer can be improved to 591 μW (at 24.576 MHz) with a peak-to-peak jitter of 1.23%. In addition, the proposed frequency synthesizer can be implemented with standard cells, making it easily portable to different processes and very suitable for system-on-a-chip applications.

A 0.3–1.4 GHz All-Digital Fractional-N PLL With Adaptive Loop Gain Controller

A 0.3–1.4 GHz all-digital phase locked loop (ADPLL) with an adaptive loop gain controller (ALGC), a 1/8-resolution fractional divider and a frequency search block is presented. The ALGC reduces the nonlinearity of the bang-bang phase-frequency detector (BBPFD), reducing output jitter. The fractional divider partially compensates for the large input phase error caused by fractional-N frequency synthesis. A fast frequency search unit using the false position method achieves frequency lock in 6 iterations that correspond to 192 reference clock cycles. A prototype ADPLL using a BBPFD with a dead-zone-free retimer, an ALGC, a fractional divider, and a digital logic implementation of a frequency search algorithm was fabricated in a 0.13- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu{\hbox {m}}$</tex></formula> CMOS logic process. The core occupies 0.2 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\hbox {mm}}^{2}$</tex> </formula> and consumes 16.5 mW with a 1.2-V supply at 1.35-GHz. Measured RMS and peak-to-peak jitter with activating the ALGC are 3.7 ps and 32 ps respectively.

Frequency search algorithm for estimating polyharmonic signal model parameters

A frequency search algorithm for estimating polyharmonic signal model parameters is considered. The algorithm uses the symmetry property of functionals of residual partial sums. The proposed frequency search algorithm provides a decrease in the amount of calculation. The efficiency of solving the estimation problem is determined.

A Novel Fast-Lock-in Digitally Controlled Phase-Locked Loop

A novel fast lock-in digitally controlled phase-locked loop (DCPLL) is proposed in this letter. This DCPLL adopts a novel frequency search algorithm to reduce the lock-in time. Furthermore, to reduce the power consumption, the frequency divider is reused as a frequency detector during the frequency acquisition, and reused as a time-to-digital converter module during the phase acquisition. To verify the proposed algorithm and architecture, a DCPLL design is implemented by SMIC 0.18µm 1P6M CMOS technology. The Spice simulation results show that the DCPLL can achieve frequency acquisition in 3 reference cycles and complete phase acquisition in 11 reference cycles when locking to 200MHz. The corresponding power consumption of DCPLL is 3.71mW.