Abstract
A blind frequency and phase search algorithm for joint frequency and phase recovery is introduced. The algorithm achieves low complexity due to processing in polar coordinates, which reduces the amount of multiplications. We show an implementation for real-time processing at 32 GBd on FPGA hardware. The hardware design allows for dynamic multi-format operation, where the format can be switched flexibly after each clock cycle (250 MHz, 128 Symbols) between 4QAM, 8QAM, and 16QAM. The performance of the algorithm is evaluated with respect to laser phase noise, carrier frequency offset, and carrier frequency offset drift. The effect of working with limited hardware resources is investigated. An FPGA implementation shows the feasibility of our carrier recovery algorithm with a negligible penalty when compared to a floating point simulation.
Highlights
An efficient multi-format carrier recovery is an essential processing block in coherent receivers for future elastic optical networks (EON) [1,2]
We present a real-time, flexible, blind, and joint carrier phase recovery (CPR) [22] and carrier frequency recovery (CFR) [23] algorithm that operates in polar coordinates for operation with low complexity
We have introduced a joint multi-format frequency and phase recovery algorithm relying on processing in polar coordinates for low hardware complexity and demonstrated its operation at 32 GBd
Summary
An efficient multi-format carrier recovery is an essential processing block in coherent receivers for future elastic optical networks (EON) [1,2]. Both approaches have already been demonstrated in real-time at low symbol rates [15] Another group of CPR algorithms takes advantage of a nonlinear transformation of the received signal. A flexible, blind, and joint CFR and CPR that operates in real-time with low hardware complexity at highest data rates has not yet been shown. This in part is because such hardware implementations in coherent optical communication links with >100 Gbit/s are challenging as the hardware has to process several 100 Gbit/s to Tbit/s of raw data at DSP clock frequencies that typically operate below 1 GHz. massive parallel processing is required [21]. The complexity and hardware requirements have been studied for an FPGA-based prototyping platform with Vivado design tools (Xilinx)
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