Frequency Compensation Scheme Research Articles

A low‐power low‐dropout regulator with improved transient response and power supply rejection

SummaryA high‐precision fast‐settling low‐dropout (LDO) regulator has been presented in this paper. A novel frequency compensation scheme has been proposed to acquire wider bandwidth while sufficient stability is guaranteed for all loading conditions without using external compensation capacitors. Moreover, novel auxiliary circuits have been proposed to improve the slew rate and minimize the settling time. The new LDO has been designed in a standard 0.18‐μm CMOS process. Postlayout simulation results show that the LDO achieves 2.7‐ and 2.48‐MHz unity‐gain frequency for 100 and 0 mA of load current, respectively, while the minimum phase margin is 64°. The results also demonstrate that the worst‐case settling time is almost equal to 1.95 μs. It is shown that by using the new slew rate enhancement technique, the settling time has been reduced from 18 to 1.9 μs. The LDO consumes a quiescent current of 21.5 μA, and the power supply rejection is −46 dB at 10‐kHz offset, which makes the LDO capable of adequately suppressing input supply ripples. The large loop gain of the proposed circuit improves the accuracy of the LDO, and the load and line regulations are 0.1 mV/mA and 0.1 mV/V, respectively.

A Novel Frequency Compensation Scheme for Heavy Load LDO with Improved Load Regulation and High Open Loop Gain

This paper presents a novel frequency compensation scheme for the stability of low dropout regulator (LDO). The proposed compensation scheme introduces a zero in the voltage regulation loop to enlarge gain and phase margin at high‐frequencies. As a result, high open‐loop‐gain and improved load regulation performances are achieved, and a particular resistor is introduced in the compensation structure to cancel the voltage drop originating from cable resistances at the output to further improve the load regulation performance. The proposed LDO with wide input/output range and high‐power supply rejection is designed and implemented in a 180 nm CMOS process. The LDO operates with an input voltage range of 4–16 V, an output voltage range of 1.5–5 V and an output current range of 0–1000 mA. High open loop gain and high bandwidth are achieved, and the simulated performances of load regulation and line regulation are less than 32 μV/mA and less than 3 mV/V over the whole operation range, respectively. The on‐chip compensation capacitor required by the compensation module is only 1.8 pF. © 2023 Institute of Electrical Engineers of Japan. Published by Wiley Periodicals LLC.

A 50 dB high-gain operational amplifier integrated with metal-oxide TFTs

This paper presents a 50 dB high-gain operational amplifier (OPAMP), which is fabricated by unipolar n-type indium–zinc–oxide thin-film transistors. Different positive feedback technologies are employed to achieve sufficient voltage gain. The fabricated OPAMP exhibits an open-loop voltage gain (A v) of 50 dB over a −3 dB bandwidth of 15 kHz at the supply voltage of 20 V. The measured unity-gain frequency (f UG) and the DC power consumption are 500 kHz and 8.07 mW, respectively. In addition, an effective frequency compensation scheme is also introduced and simulated. The simulation results that the proposed OPAMP has a voltage gain of 50 dB with 60° phase margin at 150 kHz unity-gain frequency after compensation.

Low-Complexity Sampling Frequency Offset Estimation and Compensation Scheme for OFDM-Based UWOC System

In this paper, a simple sampling frequency offset (SFO) estimation and compensation scheme based on two phase-conjugated pilots is proposed and experimentally demonstrated in an OFDM-based underwater wireless optical communication (UWOC) system. The phase shift is obtained by simple multiplication for phase-conjugated pilots, and the results are averaged to perform more accurate phase estimation. The experimental results show that the estimation offset is limited within ±3 ppm when the SFO ranges from −1000 ppm to +1000 ppm over a 1 m tap water channel. Moreover, with the help of the proposed scheme, up to ±300 ppm SFO can be well-compensated with error vector magnitude (EVM) penalties below 1 dB after 1 m underwater transmission. In addition, the results demonstrate that, compared with the ideal case without SFO, our proposed SFO compensation scheme can provide nearly negligible bit error rate (BER) penalties in saltwater with the highly scattering property.

A capacitor-free fast-response low-dropout voltage regulator

An off-chip capacitor-free low-dropout (LDO) regulator using an improved frequency compensation scheme is proposed. The proposed LDO regulator employs a class-AB error amplifier and a load-current tracker. Outstanding line regulation, load regulation and transient response are achieved. SPICE simulation based on SMIC 0.35 µm CMOS technology shows that the proposed LDO regulator has a low frequency gain over 100 dB and a unity-gain bandwidth in the MHz range. In terms of transient response, the 1% settling time is shorter than 0.2 µs.

Improved Differential Phase Detecting Optical Fiber Interferometer With a Low-Frequency Compensation Scheme

To overcome the poor low-frequency response sensitivity of differential phase detecting interferometer, an improved differential phase detecting optical fiber interferometer with a time domain low frequency compensation scheme is designed and implemented, effectively compensating the low frequency loss of the system by means of recursive accumulation method. Theoretical derivation and experimental verification are conducted in this paper. The experimental results indicate that the improved system can significantly enhance the amplitude of 10 Hz signal and signals with high fidelity can be obtained because the compensated system responds equally both to the high and low frequency signals. Further experiments in the buried pipelines monitoring reveal that the signal-to-noise ratio is obviously improved by 22 dB approximately compared with the traditional system. The positioning error of the proposed system is within ±20 m along a 40 km sensing fiber. The differential phase detection interferometer compensated by the proposed scheme has potential application in low-frequency fields such as seismic wave detection, hydrophones, sonar, pipeline monitor and geological detection.

High-Performance Multi-Stage CMOS OTA Design Using Differential Block as Compensation Network

This work presents an effective and straightforward frequency compensation scheme in CMOS three-stage amplifiers. Using a differential block in the compensation network, the proposed circuit shows independent and large first dominant pole regarding the DC gain path. The presented three-stage architecture is frequency-compensated just by a single Miller capacitor. Mathematical analysis is presented along with ample simulations that are performed using TSMC 0.18-[Formula: see text]m CMOS technology. According to the results, the proposed circuit shows DC gain equal to 118[Formula: see text]dB, GBW equal to 466[Formula: see text]MHz, PM equal to 74.3∘ and 1.2[Formula: see text]mW as power consumption, respectively. The high values of DC gain and GBW make the proposed amplifier appropriate for more speedy operations such as high-speed modulators and data converters.

A Single BJT Bandgap Reference With Frequency Compensation Exploiting Mirror Pole

In this article, we propose a bandgap reference (BGR) with a single bipolar junction transistor (BJT) branch and a proportional-to-absolute-temperature (PTAT)-embedded amplifier. Having fewer BJT and passive components, the proposed BGR uses less power and area compared to the conventional BGR that uses multiple BJTs and resistors. As the proposed BGR achieves temperature compensation by employing a feedback loop that has two gain stages, frequency compensation is required. We propose frequency compensation scheme where a compensation capacitor is connected between the BGR output and a current mirror node in the PTAT-embedded amplifier. By using this scheme, location of a mirror pole associated with the current mirror node can be optimized to achieve both improved stability and low power consumption. Fabricated in 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS, the proposed BGR achieves temperature coefficient of 26.3 ppm/°C over −40 °C–140 °C; voltage accuracy ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sigma /\mu $ </tex-math></inline-formula> ) of 0.33%; and power supply rejection (PSR) of −52 dB, −44 dB at 100 Hz, 1 MHz respectively; while occupying 0.0082 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consuming 192 nW without startup circuit and trimming.

High-Speed CMOS Three-Stage Amplifier Based on Feedback Attenuation

This paper presents a new and simple frequency compensation scheme for multistage CMOS operational transconductance amplifiers (OTAs). In this work, by applying a differential block frequency compensation (DBFC) technique to a compensation network of three-stage OTA, the dominant pole is drastically improved independent from the DC gain path. The DBFC introduces amplified signal directly to the second-stage output through the compensation capacitor. The signal injection increases operational frequency range while just a single and small value capacitor is used as the Miller capacitor, which leads to considering the proposed configuration as a low die area occupation and high-speed amplifier. The simulation results show with the same capacitive load and power dissipation the gain bandwidth (GBW) frequency can be improved considerably compared to conventional nested Miller compensation. The presented circuit is simulated in a 0.18[Formula: see text][Formula: see text]m CMOS technology with a 1.8[Formula: see text]V supply voltage. According to the results, the proposed circuit shows 102[Formula: see text]dB, 105[Formula: see text]MHz, and 343[Formula: see text][Formula: see text]W as the DC gain, GBW, and power consumption, respectively.

A 2 mA PA Driver Capable of Handling 1μF Load Capacitance with a Three-Stage Class-AB Rail-To-Rail Amplifier

In this paper, a three-stage rail-to-rail class-AB amplifier for GaAs/GaN PA driver in radar transmitter components is achieved using a proposed frequency compensation scheme in 0.35 μm CMOS technology. Meanwhile, a negative voltage reference is proposed with low un-trimmed spread by employing level shift technique. The PA driver capable of handling load capacitance ranging from no load to 1uF only consumes 2 mA of quiescent current while delivering a peak current of 100 mA to the load with −90 dB THD. The core area occupies 2.4mm2.

A Simple Blind Sampling Frequency Offset Estimation Scheme for Short-Reach DD-OFDM Systems

In this paper, a simple and overhead-free sampling frequency offset (SFO) blind estimation and compensation scheme is proposed and experimentally demonstrated in a short-reach direct detection orthogonal frequency division multiplexing (DD-OFDM) transmission system. After extracting subcarriers of OFDM symbols from multiple OFDM frames, the phase shift is obtained by the fourth-power algorithm, and the obtained results are averaged to perform phase estimation. It can achieve high-precision SFO estimation while ensuring low computational complexity as well as high spectral efficiency. The experimental results show that the SFO estimation accuracy using the proposed scheme can be significantly reduced to as low as ±3 ppm when SFO ranges from -1000 ppm to +1000 ppm after 20-km standard single-mode fiber (SSMF) transmission. Moreover, for the QPSK/16QAM encoded DD-OFDM systems aided by the proposed scheme, up to ±200 ppm SFO can be compensated with slight error vector magnitude (EVM) penalties after 20-km SSMF transmission. Furthermore, the results demonstrate that despite the existence of severe SFO, our proposed SFO compensation scheme can offer nearly negligible power penalties in the DD-OFDM system with optical back-to-back (OBTB) and 20-km SSMF transmission as compared to the ideal case without SFO.

A Multi-Loop Slew-Rate-Enhanced NMOS LDO Handling 1-A-Load-Current Step With Fast Transient for 5G Applications

Compact low dropout (LDO) with high current handling capability and superior transient response is gaining increasing attention for the battery-powered 5G mobile applications. In this article, a new multiple-loop design technique for fast-transient response LDO regulator design has been proposed and successfully implemented in a 0.13- $\mu \text{m}$ SOI CMOS process for portable smartphone and tablet PC applications. Its supply current capacity is more than 1 A, and its output voltage is from 1.2 to 1.8 V. The proposed LDO features a 10-mV undershoot and overshoot with 1-A/100-ns load current on a 1- $\mu \text{F}$ output capacitor. This superior transient performance is achieved by embodying a novel frequency compensation scheme without penalty of dc loop gain drop in large load current conditions. The dc loop gain is 60 dB and constant regardless of the fact that the load current varies from 0 to 1 A. This contributes to a small load regulation and line regulation of 0.6 $\mu \text{V}$ /A and 0.23 mV/V, respectively. The LDO consumes 35- $\mu \text{A}$ quiescent current in the mission mode and 5 $\mu \text{A}$ in the standby mode. The LDO silicon size is 325 $\mu \text{m}\,\,\times $ 106 $\mu \text{m}$ .

Dual Active-Feedback Frequency Compensation for Output-Capacitorless LDO With Transient and Stability Enhancement in 65-nm CMOS

An output-capacitorless low-dropout regulator (OCL-LDO) using a dual-active feedback frequency compensation (DAFFC) scheme with both transient and stability enhancement has been presented in this paper. The DAFFC scheme consists of two parallel active feedback paths, which creates two pole-zero pairs to effectively enhance the stability and transient response for the proposed OCL-LDO. Compared to the conventional single-path active-feedback frequency compensation method, the proposed DAFFC technique has provided one more design freedom with one more active feedback loop deployed and has been proved to be capable of obtaining better compensation effects with the same capacitor budget. Besides, the induced extra ac currents by the two active feedback loops have also enhanced the transient response of the proposed OCL-LDO. To substantiate the proposed DAFFC, a telescopic cascode output stage for error amplifier, and two on-chip compensation capacitors (5 and 1 pF, respectively) are needed. The proposed OCL-LDO has been implemented in 65-nm CMOS technology and the active chip area is 0.0105 mm2. The output voltage is 0.8 V, and the minimum input voltage is 0.95 V at 100-mA loading current. The proposed OCL-LDO can work stably in a load range of 0 to 100 mA with 14-μA quiescent current.

A reliable model for the compensation loop of multistage amplifiers at high frequency

PurposeMultistage amplifiers require a reliable frequency compensation solution to remain stable in a closed-loop configuration. A frequency compensation scheme creates an inner negative feedback loop amongst different amplifying stages and shapes the frequency response such that an unconditionally stable single-pole amplifier results for closed-loop operation. The frequency compensation loop is thus responsible for the placement of the poles and zeros and the final stability of multistage amplifiers. An amplifier incorporating a sophisticated frequency compensation network cannot be, however, analyzed in the presence of a complex ac feedback loop. The purpose of this study is to provide a reliable model for the compensation loop of multistage amplifiers at the higher frequencies.Design/methodology/approachIn this paper, the major part of the amplifier, including a two-port network comprising the compensation network, is characterized using a reliable feedback model.FindingsThe model integrates all the frequency-dependent components of the frequency compensation network, and it can evaluate the nondominant real or complex poles of an amplifier.Originality/valueThe reliability of the proposed model is verified through analysis of the frequency response of the amplifiers and by comparing the analytic results with the simulation results in standard CMOS process.

An effective SFO estimation and compensation scheme for FOFDM-based VLC systems

A simple sampling frequency offset (SFO) estimation and compensation scheme is proposed and experimentally demonstrated for fast orthogonal frequency-division multiplexing (FOFDM)-based visible light communication (VLC) systems. Experimental results indicate that, SFO ranging from −300 to 300 ppm can be accurately estimated by using the proposed scheme, with estimated error less than ±2 ppm. Meanwhile, ±200 ppm SFO-affected FOFDM signals can be successfully recovered with negligible performance penalties.

A 1-mW Class-AB Amplifier With −101 dB THD+N for High-Fidelity 16 $\Omega$ Headphones in 65-nm CMOS

A low-power class-AB amplifier for high-fidelity headphones is presented. The linearity of a class-AB amplifier strongly depends on the loop gain over the audio band and voltage swing. In this paper, a cascode-driven mesh technique limits the number of high-swing nodes in the output stage, thereby preserving the loop gain of the preceding gain stages. A frequency compensation scheme is proposed that extends the unity-gain bandwidth (UGB) and increases the loop gain at 20 kHz. Combining these two techniques, the amplifier achieves −101.4-dB total harmonic distortion plus noise (THD+N) over the full audio band, the lowest ever reported nonlinearity among sub-milliwatt CMOS class-AB amplifiers. The amplifier delivers 51.2-mW peak power to a $16\Omega \|0.33$ -nF load while consuming 0.97 mW of total static power. It has UGB of 12.3 MHz and SNR of 108 dB. These results are consistent when measured over eight test chips. Compared to the recent prior art, the amplifier exhibits >12 dB better linearity and >14-dB dynamic range. This results in 2.5 $\times $ improvement in figure of merit (FOM = Peak Load Power/(Quiescent Power $\times $ THD+N[%])). It occupies 0.16 mm 2 in a standard 65-nm CMOS.

Analysis and design of a current-mode bandgap reference with high power supply ripple rejection

In this paper, a current-mode bandgap reference (BGR) circuit with cascode current mirrors and improved frequency compensation for achieving high power supply ripple rejection (PSRR) is presented. By slightly modifying a conventional frequency compensation scheme, the PSRR of the BGR is significantly enhanced. PSRRs of the BGR with the two different compensation techniques have been formulated and verified. Moreover, design considerations are presented, taking into account the critical parasitic capacitor's effect in PSRR. To our knowledge, this is the first time in the literature of explicitly demonstrating how the PSRR of a BGR is improved due to the frequency compensation. The feedback loop stability is also analyzed. The measured PSRR of an example BGR using the modified compensation fabricated in a standard 0.18-μm CMOS process is −77dB and −62dB at 1kHz, and 100kHz, respectively, with more than 40dB improvement at the high frequency ranges over the design with the classical compensation.

High gain amplifier with feedforward compensation based on quasi-floating gate transistors

In this paper, a two-stage amplifier with feedforward frequency compensation scheme is presented. Because the frequency compensation scheme uses the amplifier's second stage gm to create the feedforward path no additional circuitry is needed. To verify the proposed scheme a prototype was fabricated using 0.5μm technology. Measurements results demonstrate a high DC gain, 18MHz of gain-bandwidth product and 86° phase margin are achieved with an output load capacitance of 80pF.

A 5.6 ppm/°C Temperature Coefficient, 87-dB PSRR, Sub-1-V Voltage Reference in 65-nm CMOS Exploiting the Zero-Temperature-Coefficient Point

This paper describes an MOSFET-only voltage reference realized in 65-nm CMOS featuring a temperature coefficient (TC) of 5.6 ppm/°C from -40 °C to 125 °C, a power supply rejection ratio of 87 dB from dc up to 800 kHz (and 75 dB at 1 MHz), a minimum supply voltage of 0.8 V, and a power dissipation of 13 μW. These attributes are achieved by exploiting the zero-TC point of an MOSFET and combining it with a novel curvature-compensation technique, an active attenuator, and an impedance-adapting frequency compensation scheme.

Evaluation of the pole expressions of nano-scale multistage amplifiers based on equivalent output impedance

Several frequency compensation schemes have been proposed to stabilize multistage amplifiers with negative feedback. The performance of these amplifiers can be analyzed by inspecting their input-output transfer function as representation of their frequency response. With many circuit elements affecting the output response, it is relatively difficult to obtain the real transfer function of multistage amplifiers based on only the original small-signal expressions. Instead, certain techniques such as Miller’s theorem are used to approximate important parameters such as DC gain and dominant pole. These methods are not generally helpful for approximating the nondominant poles which have a critical role on the loop stability of nano-scale amplifiers. With this issue in mind, this work proposes a systematic methodology to achieve the pole expressions of multistage amplifiers with frequency compensation. The key in the proposed technique is to model the equivalent impedance of the compensation loop at the output. The effectiveness of the proposed approach has been verified through comparison between the transfer functions obtained from theory and those transfer functions found in the literature.