A Multi-Loop Slew-Rate-Enhanced NMOS LDO Handling 1-A-Load-Current Step With Fast Transient for 5G Applications

Abstract

Compact low dropout (LDO) with high current handling capability and superior transient response is gaining increasing attention for the battery-powered 5G mobile applications. In this article, a new multiple-loop design technique for fast-transient response LDO regulator design has been proposed and successfully implemented in a 0.13- $\mu \text{m}$ SOI CMOS process for portable smartphone and tablet PC applications. Its supply current capacity is more than 1 A, and its output voltage is from 1.2 to 1.8 V. The proposed LDO features a 10-mV undershoot and overshoot with 1-A/100-ns load current on a 1- $\mu \text{F}$ output capacitor. This superior transient performance is achieved by embodying a novel frequency compensation scheme without penalty of dc loop gain drop in large load current conditions. The dc loop gain is 60 dB and constant regardless of the fact that the load current varies from 0 to 1 A. This contributes to a small load regulation and line regulation of 0.6 $\mu \text{V}$ /A and 0.23 mV/V, respectively. The LDO consumes 35- $\mu \text{A}$ quiescent current in the mission mode and 5 $\mu \text{A}$ in the standby mode. The LDO silicon size is 325 $\mu \text{m}\,\,\times $ 106 $\mu \text{m}$ .