Statistical Timing Analysis Framework Research Articles

Potential Critical Path Selection Based on a Time-Varying Statistical Timing Analysis Framework

Negative bias temperature instability along with the presence of process variations has resulted in time-varying path criticalities. To ensure reliable circuit operation, aging sensors are used at the end of potential critical paths (PCPs) for delay monitoring. Optimization of the number of delay sensors requires accurate computational models for prediction of criticality and selection of PCPs. We identify a path as a PCP if its maximum global criticality over the lifetime exceeds a certain threshold. However, the global criticality of a path could vary nonmonotonically over the lifetime of the device. In this paper, we propose a framework for time-varying statistical static timing analysis (TV-SSTA), wherein the circuit delay is obtained as a collection of time-varying canonicals with breakpoints in time which define the end of validity of one and the start of the next canonical. We show that the global criticality of any path will be maximum either at $t = 0$ or at these breakpoints. Hence, criticality computation and PCP selection need to be done only at these time points, which typically is less than four. The TV-SSTA is integrated with a previously proposed criticality computation technique to identify the PCPs and the results are validated against Monte Carlo simulations.

Low VDD and body bias conditions for testing bridge defects in the presence of process variations

Bridge defects are an important manufacturing defect that may escape test causing reliability issues. It has been shown that in nanometer regime, process variations pose important challenges for traditional delay test methods lowering test quality. Therefore, advances in test methodologies to enhance bridge detection are required. In this work a Statistical Timing Analysis Framework (STAF) is used to compute the probability of detection of bridge defects for different VDD and RBB values. The detection of the bridge defects of a circuit is computed by the Statistical Fault Coverage (SFC). The STAF allows to capture properly the behavior of the mean and a standard circuit delay when VDD and RBB change. Furthermore, the STAF uses a realistic bridge defect model suitable to consider appropriately the impact of VDD and RBB on delay increase. This methodology is applied to some ISCAS benchmark circuits implemented in a commercial 65nm CMOS technology. The obtained results of several ISCAS benchmark circuits show clearly that the Statistical Fault Coverage (SFC) increases significantly when VDD is lowered, and increases even more when RBB is applied at Low VDD. The test conditions to improve resistive bridge detection combining Low VDD and Reverse Body Bias (RBB) under a delay based test are determined. It is shown that the impact of RBB on bridge detection improves significantly for a sufficient low value of VDD. The values of Low VDD and RBB can be selected considering the tradeoff between fault coverage and test time penalization.

Screening small-delay defects using inter-path correlation to reduce reliability risk

Subtle defects such as low resistive vias and high resistive shorts cause Small-Delay Defects that are hard to detect even by advanced test methodologies. Detection of these defects aggravates with process variations becoming an important source of test escapes. Furthermore, these defects may degrade with time posing a reliability risk. In this paper, a novel methodology to detect SDDs in the presence of process variations using delay correlation information between logic paths of a circuit is proposed. This methodology exploits the concept that for two correlated paths, a part of the delay variance in one path can be described by the delay variance in other path. Using multiple path prediction allows to further improve the detection of SDDs. A path-based statistical timing analysis framework has been developed and implemented to compute timing information and inter-path correlation. Spatial and structural correlation, and random dopant fluctuations are considered. Simulation results in ISCAS85 benchmark circuits show that the proposed methodology is able to detect SDDs in the slack interval and to distinguish delay defects from process variations. The obtained results give indication of the promising capabilities of the proposed technique to detect “very” small-delay defects. Hence, test quality is improved leading to higher product reliability.

Process Variations-Aware Statistical Analysis Framework for Aging Sensors Insertion

As process technology continues to shrink, Process Variations and Aging effects have an increasing impact on the reliability and performance of manufactured circuits. Aging effects, namely due to Negative Bias Temperature Instability (NBTI) produce performance degradation as time progresses. This degradation rate depends on a) Operational conditions (e.g., VDD, Temperature and time of electrical stress on MOS transistors) and b) Static technological parameters defined in the fabrication process. Moreover, performance of electronic systems for safety-critical applications which operate for many years in harsh environments are more prompt to be impacted by aging. In order to guarantee a safe operation in advanced technologies, aging monitoring should be performed on chip using built-in aging sensors. The purpose of this work is to present a methodology to determine the correct location for aging sensor insertion, considering the combined impact of process variations (PV) and aging effects (namely due to NBTI). In order to implement the methodology, a path-based statistical timing analysis framework and tools have been developed. It is shown that delay path reordering, associated with PV and aging, may justify the insertion of a few additional sensors, to cover abnormal delays of signal paths that become critical, under long system operation (e.g., 10 years).

The Impact of BTI Variations on Timing in Digital Logic Circuits

A new framework for analyzing the impact of bias temperature instability (BTI) variations on timing in large-scale digital logic circuits is proposed in this paper. This approach incorporates both the reaction-diffusion model and the charge-trapping model for BTI and embeds these into a temporal statistical static timing analysis framework capturing process variations and path correlations. Experimental results on 32-, 22-, and 16-nm technology models, which were verified through Monte Carlo simulation, confirm that the proposed approach is fast, accurate, and scalable and indicate that BTI variations make a significant contribution to circuit-level timing variations.

An accurate sparse-matrix based framework for statistical static timing analysis

Statistical static timing analysis has received wide attention recently and emerged as a viable technique for manufacturability analysis. To be useful, however, it is important that the error introduced in SSTA be significantly smaller than the manufacturing variations being modeled. Achieving such accuracy requires careful attention to the delay models and to the algorithms applied. In this paper, we propose a new sparse-matrix based framework for accurate path-based SSTA, motivated by the observation that the number of timing paths in practice is sub-quadratic based on a study of industrial circuits and the ISCAS89 benchmarks. Our sparse-matrix based formulation has the following advantages: (a) it places no restrictions on process parameter distributions; (b) it can use an accurate polynomial-based delay model which takes into account slope propagation naturally; (c) it takes advantage of the matrix sparsity and high performance linear algebra for efficient implementation. Our experimental results are very promising.

LEAKAGE POWER REDUCTION THROUGH DUAL Vth ASSIGNMENT CONSIDERING THRESHOLD VOLTAGE VARIATION

With technology scaling, leakage power has become an important part of the total power consumption, affecting both yields and lifetime of digital circuits. Dual V th assignment, which was an effective method to reduce leakage power in the past, is also effective in today's technologies with certain modifications. In this paper, based on our statistical timing analysis (SSTA) framework, we presented a dual V th assignment method which can effectively reduce the leakage power even in the presence of large V th variation. Besides, taking the correlation between gates into account, we propose a novel statistical DAG pruning method to speed up the dual V th assignment algorithm. Experimental results show that statistical dual V th assignment can reduce on average 95% and 40% more leakage current compared with the conventional static method, without affecting the performance constraints under 180 nm and 90 nm technology nodes. Also our statistical DAG pruning method can reduce 30% gates in the circuit on average and save up to 50% of the total runtime in the 90 nm technology node.

A Quadratic Modeling-Based Framework for Accurate Statistical Timing Analysis Considering Correlations

The impact of parameter variations on timing due to process variations has become significant in recent years. In this paper, we present a statistical timing analysis (STA) framework with quadratic gate delay models that also captures spatial correlations. Our technique does not make any assumption about the distribution of the parameter variations, gate delays, and arrival times. We propose a Taylor-series expansion-based quadratic representation of gate delays and arrival times which are able to effectively capture the nonlinear dependencies that arise due to increasing parameter variations. In order to reduce the computational complexity introduced due to quadratic modeling during STA, we also propose an efficient linear modeling driven quadratic STA scheme. We ran two sets of experiments assuming the global parameters to have uniform and Gaussian distributions, respectively. On an average, the quadratic STA scheme had 20.5times speedup in runtime as compared to Monte Carlo simulations with an rms error of 0.00135 units between the two timing cummulative density functions (CDFs). The linear modeling driven quadratic STA scheme had 51.5times speedup in runtime as compared to Monte Carlo simulations with an rms error of 0.0015 units between the two CDFs. Our proposed technique is generic and can be applied to arbitrary variations in the underlying parameters under any spatial correlation model

Statistical Timing Analysis With Coupling

As technology scales to smaller dimensions, increasing process variations and coupling induced delay variations make timing verification extremely challenging. In this paper, the authors establish a theoretical framework for statistical timing analysis with coupling. They prove the convergence of their proposed iterative approach and discuss implementation issues under the assumption of a Gaussian distribution for the parameters of variation. A statistical timer based on their proposed approach is developed and experimental results are presented for the International Symposium on Circuits and Systems benchmarks. They juxtapose their timer with a single pass, noniterative statistical timer that does not consider the mutual dependence of coupling with timing, and another statistical timer that handles coupling deterministically. Monte Carlo simulations reveal a distinct gain (up to 24%) in accuracy by their approach in comparison to the others mentioned

Delay defect diagnosis based upon a statistical timing model – the first step

The problem of diagnosing delay defects is defined using a statistical timing model. The differences between delay defect diagnosis and traditional logic defect diagnosis are illustrated. Different diagnosis algorithms are proposed and their performance evaluated via statistical defect injection and statistical delay fault simulation. With a statistical timing analysis framework developed in the past, new concepts in delay defect diagnosis are demonstrated and experimental results are discussed based upon benchmark circuits.