Low VDD and body bias conditions for testing bridge defects in the presence of process variations

Abstract

Bridge defects are an important manufacturing defect that may escape test causing reliability issues. It has been shown that in nanometer regime, process variations pose important challenges for traditional delay test methods lowering test quality. Therefore, advances in test methodologies to enhance bridge detection are required. In this work a Statistical Timing Analysis Framework (STAF) is used to compute the probability of detection of bridge defects for different VDD and RBB values. The detection of the bridge defects of a circuit is computed by the Statistical Fault Coverage (SFC). The STAF allows to capture properly the behavior of the mean and a standard circuit delay when VDD and RBB change. Furthermore, the STAF uses a realistic bridge defect model suitable to consider appropriately the impact of VDD and RBB on delay increase. This methodology is applied to some ISCAS benchmark circuits implemented in a commercial 65nm CMOS technology. The obtained results of several ISCAS benchmark circuits show clearly that the Statistical Fault Coverage (SFC) increases significantly when VDD is lowered, and increases even more when RBB is applied at Low VDD. The test conditions to improve resistive bridge detection combining Low VDD and Reverse Body Bias (RBB) under a delay based test are determined. It is shown that the impact of RBB on bridge detection improves significantly for a sufficient low value of VDD. The values of Low VDD and RBB can be selected considering the tradeoff between fault coverage and test time penalization.