FRAM Technology Research Articles

Ferroelectric memory: state-of-the-art manufacturing and research

Semiconductor industry calls for emerging memory, demonstrating high speed (like SRAM or DRAM), nonvolatility (like Flash NAND), high endurance and density, good scalability, reduced energy consumption and reasonable cost. Ferroelectric memory FRAM has been considered as one of the emerging memory technologies for over 20 years. FRAM uses polarization switching that provides low power consumption, nonvolatility, high speed and endurance, robust data retention, and resistance to data corruption via electric, magnetic fields and radiation. Despite the advantages, market share held by FRAM manufacturers is insignificant due to scaling challenges. State-of-the-art FRAM manufacturing is studied in this paper. Ferroelectric capacitors and memory cells made by main commercial FRAM manufactures (Texas Instruments, Cypress Semiconductor, Fujitsu и Lapis Semiconductor) are explored. All memory cells are based on the lead zirconate titanate PZT capacitor with the thickness of about 70 nm and IrOx/Ir or Pt electrodes. The leading FRAM technology remains the 130 nm node CMOS process developed at Texas Instruments fabs. New approaches to further scaling and new devices based on ferroelectrics are reviewed, including binary ferroelectrics deposited by ALD techniques, piezoelectronic transistors, ferroelectric/2D-semiconductor transistor structures, and others. Whether FRAM technology will be able to resolve one of the main contradictions between a high-speed processor and a relatively slow nonvolatile memory depends on the success of the new technologies integration.

INNOVATION IN 1T1C FRAM TECHNOLOGIES FOR ULTRA HIGH RELIABLE MEGA DENSITY FRAM AND FUTURE HIGH DENSITY FRAM

ABSTRACT FRAM whose cell structure and operation is almost identical to DRAM, can ideally realize cell size and performance of DRAM. However, the density and performance of current FRAM still fall far behind those of DRAM. In this paper, innovative 1T1C FRAM technologies for ultra high reliable mega density FRAMs and future high density FRAMs are discussed. A novel electrode technology has been proved to guarantee 175°C, 10 years retention lifetime and more than 1E13 endurance lifetime of mega density 1T1C, COB FRAM with the cell size of 15F2 at 250 nm technology node. Furthermore, a cell size of 12F2 at 150 nm technology node has successfully been realized by developing innovative 200 nm thick capacitor stack technologies and novel capacitor etching technologies. Finally, critical issues of 3-D capacitor arising from 3-dimensional deposition, such as step coverage and film uniformity have been greatly improved by the modification of the MOCVD PZT feeding source and a newly introduced noble metal atomic layer deposition technology.

Current and Future High Density FRAM Technology

Current high density FRAM devices have been fabricated by developing several novel integration technologies such as capacitor technology and process technology. The process technology minimizes the integration degradation using stable BC scheme, encapsulating barrier layer (EBL), and effective etching curing process. The capacitor technology generates robust ferroelectric capacitors to be immune to any integration damage by taking advantage of new ferroelectric films and CVD deposition technique. Future FRAM technology will be focused on etchless scheme, nano-scale ferroelectric films, and three-dimensional capacitor scheme using CVD deposition techniques for noble metal electrode with excellent step coverage, which will produces high density 256 Mb FRAM and beyond.

Novel Common Cell Via and Etch Stopper Technology for 0.25 μM 1T1C 32 MBIT FRAM

In the 0.25 μm FRAM technology generation, it is extremely difficult to define the hole-type cell via on very small top electrode area, because there is no process margin for the hole type cell via. Therefore, a runner via technology based on line-type cell via with Ir etch stopper is developed for 0.25 μm FRAM technology generation. However, it was found that the severe charge degradation occurred during the runner cell via process. It was found that the stress of Ir film plays a dominant role in degrading the capacitor value. Since the Ir film shows severe severe stress variation from compressive to tensile during heating and cooling, the ferroelectric capacitors using the Ir etch stopper show the charge degradation during integration. Therefore, we developed a common cell via scheme and stable PE-SiN etch stopper which possess compressive stress and high etching selectivity against PSG film for replacing Ir etch stopper. The polarization value of ferrolectric capacitor was not degraded after etch-stopper process. The 0.25 μm ferroelectric capacitors exhibited excellent P r value of 15 μC/cm2 after completing whole process integration, which guarantees a reliable high yield.

Current Status of Fram Development and Future Direction

Current and future FRAM technologies are reviewed and discussed for developing high density FRAM devices as stand-alone memory application. In order to enter into mainstream of memory devices, FRAM devices should achieve such small cell size factor of ∼8F 2 , strong reliability, and design optimization. The low cell size factor can be realized by using etchless capacitor technology, ultra thin capacitor technology, and runner via technology. The reliability can be acquired by Pt-inserting technology. Finally, high density FRAM device can be accomplished by design optimization.

Degradation of Pt/PLZT/Pt capacitors caused by hydrogen in interlayer dielectrics

A correlation between ferroelectric properties of the PLZT capacitors and amount of H2 and H2O gasses desorbed from interlayer dielectrics were investigated quantitatively. H2 and H2O gasses desorbed from interlayer dioxides were analyzed using thermal desorption spectroscopy. Polarization charges and its aging characteristics of memory array capacitors with area of 2 μm squares did not depend on amount of desorbed H2 explicitly, but strongly on H2O desorption. It is considered that silanol and hydroxyalkyl groups worked as hydrogen donor with catalytic activities of Pt top electrodes. As a result, hydrogen atoms should work as a major degradation agent for the imprint phenomena of memory array capacitors. Precise control of hydroxyl groups contained in the interlayer dielectrics and passivation films resulted in very small retention degradation caused by imprint phenomena, and realized high reliability and high density FRAM technologies.

Technology perspective for 1T/1C fram

The ideal properties of ferroelectric material as data storage element have drawn much attention. Recent rapid advances of FRAM technology have demonstrated that FRAM has great possibility of memory application. However, in spite of the rapid progress in FRAM technology, FRAM devices can not compete with their counterparts of memory devices because they do not have cost-effectiveness. In this paper, current FRAM technology is firstly reviewed, and near future FRAM technology is discussed. Future FRAM technology is directed for highly cost-effective FRAM devices with suggestion of a candidate future FRAM technology.

A reactive ion etch study for producing patterned platinum structures

Various high-density DRAM and FRAM technologies currently under investigation utilize high-dielectric constant materials requiring noble metal or refractory metal oxide electrodes. In this paper we describe a study of platinum patterning by reactive ion etching (RIE). Platinum films were etched in a rf diode parallel plate RIE tool with a grounded upper electrode and a 13.56 rf powered lower electrode upon which substrates were processed. The removal characteristics of blanket platinum films and platinum films with a patterned photoresist etch mask were investigated as a function of gas chemistry (Ar, CF4, SF6, and Cl2), rf power (100 to 680 W), gas pressure (5 to 100 mTorr), total gas flow (5 to 80 scan), and substrate temperature (21 to 300°C). The platinum etch was characterized in terms of etch rate, amount of redeposited material observed on the photoresist etch sidewalls (‘fencing'), and etch scale-up non-uniformity versus small size and feature size. Platinum etch rates from 80 to 1250 Å/minute were observed with corresponding substrate dc bias voltages of -500 to -1600 V. A computer program was developed to model the etch process. Computer modeling results were correlated with etched structures to optimize the etch process conditions. Optical emission spectroscopy (OES) was utilized to observe gas phase plasma species for chemical etching determination, and optimized as an optical endpoint monitor. Auger electron spectroscopy (AES) was implemented in chemically analyzing the redeposited ‘fence’ material. Using selected RIE process conditions, platinum films with a patterned photoresist etch mask were etched resulting in clean, residue-free structures with sidewall angles approximately 29°. Best process to date using a post-RIE cleanup yields sidewall angles approximately 69°.