Fractional Phase-locked Loop Research Articles

A low jitter fractional PLL with offset current charge pump

A low jitter fractional phase-locked loop (PLL) with high quality local oscillator signal for RF transceiver is presented in this paper. Compared with the traditional structure, not only the gated-offset linearization technique is adopted to improve the linearity of the charge pump (CP), but also the sampling filter is used to further reduce the output ripple of the charge pump. The voltage-controlled oscillator (VCO) adopts the tail resistor and second harmonic filter structure to reduce its noise level. The circuit is implemented in a standard 28 nm CMOS process, and the reference clock frequency is 95.76 MHz, which is provided by an integrated crystal oscillator. The chip test results show that the locking frequency range of the PLL is located between 2.42GHz and 3.27 GHz. The phase noise measured at the center frequency of 3.27 GHz at 1 MHz frequency offset is −122 dBc/Hz, RMS jitter is 286 fs, the chip area is 0.78 mm2, and the core current consumption of the PLL is 67.2 mA.

Acoustic detection of bearing faults through fractional harmonics lock-in amplification

Bearing failure detection in induction motors is vital to prevent breakdowns and dead times in industrial processes. Non-invasive detection of bearing faults can be performed by analyzing sound signals and the associated spectral signature. However, measured sound often contains signals from other surrounding sources of vibrations, which can pollute analysis or degrade SNR. This work proposes the use of Lock-In Amplification (LIA) for bearing fault detection in order to overcome SNR limitations and allow specific detection.In practice, LIA is synchronized to the motor shaft frequency through a fractional Phase-locked loop (PLL) frequency synthesizer, delivering characteristic frequencies for bearing faults, which are fractional harmonics of the shaft rotation frequency, and phase-locked to the motor under study.Comparison with Fourier spectrum measurements confirms the superior ability of LIA for extracting small signals from noise, but also allows specific detection, even in the presence of external sources vibrating at the same frequencies as the motor of interest. Additionally, fractional harmonics LIA was able to detect characteristic frequencies from fault-free conditions, paving the way for earlier failure detection and continuous monitoring.This work is the first reported experimental implementation of fractional harmonics LIA for bearing fault detection purposes.

A CMOS RF Receiver with Improved Resilience to OFDM-Induced Second-Order Intermodulation Distortion for MedRadio Biomedical Devices and Sensors

A MedRadio RF receiver integrated circuit for implanted and wearable biomedical devices must be resilient to the out-of-band (OOB) orthogonal frequency division modulation (OFDM) blocker. As the OFDM is widely adopted for various broadcasting and communication systems in the ultra-high frequency (UHF) band, the selectivity performance of the MedRadio RF receiver can severely deteriorate by the second-order intermodulation (IM2) distortion induced by the OOB OFDM blocker. An analytical investigation shows how the OFDM-induced IM2 distortion power can be translated to an equivalent two-tone-induced IM2 distortion power. It makes the OFDM-induced IM2 analysis and characterization process for a MedRadio RF receiver much simpler and more straightforward. A MedRadio RF receiver integrated circuit with a significantly improved resilience to the OOB IM2 distortion is designed in 65 nm complementary metal-oxide-semiconductor (CMOS). The designed RF receiver is based on low-IF architecture, comprising a low-noise amplifier, single-to-differential transconductance stage, quadrature passive mixer, trans-impedance amplifier (TIA), image-rejecting complex bandpass filter, and fractional phase-locked loop synthesizer. We describe design techniques for the IM2 calibration through the gate bias tuning at the mixer, and the dc offset calibration that overcomes the conflict with the preceding IM2 calibration through the body bias tuning at the TIA. Measured results show that the OOB carrier-to-interference ratio (CIR) performance is significantly improved by 4–11 dB through the proposed IM2 calibration. The measured maximum tolerable CIR is found to be between −40.2 and −71.2 dBc for the two-tone blocker condition and between −70 and −77 dBc for the single-tone blocker condition. The analytical and experimental results of this work will be essential to improve the selectivity performance of a MedRadio RF receiver against the OOB OFDM-blocker-induced IM2 distortion and, thus, improve the robustness of the biomedical devices in harsh wireless environments in the MedRadio and UHF bands.

Current pulse shaping technique for low spur fractional‐N phase‐locked loop

Current pulse shaping technique is proposed for low spur fractional-N phase-locked loop, which is realised by a variable amplitude charge pump (VA-CP) and a fixed-position, fixed-width and variable-period pulse generator (FFVPG). The current pulse of VA-CP driven by the FFVPG is shaped to fixed position, fixed width, variable amplitude and variable period for eradicating both reference spurs and fractional spurs. The period of VA-CP's current pulse is T REF during transient and N 1 × T REF during locking status, in which the N 1 should be properly set in order to reduce fractional spurs as far as possible and accelerate locking time. The spur performance of the proposed fractional phase-locked loop is evaluated by analysing the spectrum of tuning voltage when reference frequency is 20 MHz and division ratio is 120.13. Spectre based simulation results show the reference spurs at integer multiplies of 20 MHz is eradicated, and the fractional spurs at 10 MHz and the other fractional frequencies are 19.67 dB and much less than that with the existing technique, which verify the feasibility of this study.

Spur reduction architecture for multiphase fractional PLLs

In this study, a multiphase fractional phase-locked loop (PLL) is presented with methods to reduce spurs. General causes of spurs are non-idealities of the phase-frequency detector (PFD) and charge pump (CP) and phase errors between the adjacent phases from the oscillator. In the architecture, the non-idealities of the PFD and CP are compensated and a phase correction circuit is added after the oscillator phase generator to reduce the phase errors, and hence minimise the spurs. Spurs may still be persistent after these modifications due to process variations and device mismatch. The effect is visible in the perturbations of the loop filter control voltage. The residual spurs are minimised by further filtering the control voltage using a moving average filter and then applying it to the oscillator. The PLL is designed in 180 nm technology and outputs a 400 MHz carrier. The highest fractional spur is decreased from −36 to −66 dBc through phase correction and control voltage filtering.

A System-on-Chip Crystal-Less Wireless Sub-GHz Transmitter

This paper presents a fully integrated system-on-chip wireless transmitter that has no need for an external quartz crystal frequency reference. Instead, a nontrimmable $LC$ oscillator (LCO) is implemented, operating at a fixed frequency of roughly 3.2 GHz. This LCO serves as the accurate frequency reference of the transmitter and is used to derive a frequency in the sub-GHz range for wireless applications via a fractional phase-locked loop. The digital functionality required for the frequency generation and thus for the wireless operation is performed by an 8-b microcontroller. The calibration data as well as the application specific firmware are stored in an integrated EEPROM. An initial frequency accuracy of ±52 ppm over a temperature of −20 °C to 85 °C is achieved using only two temperature insertions for the calibration. The device covers a continuous frequency range of 10–960 MHz and provides an ASK and GFSK operation. A low harmonic power amplifier was implemented to overcome design issues due to injection modulation effects. The chip is implemented in a 130 nm standard CMOS process and constitutes a new approach for a fully integrated wireless sub-GHz transmitter that is competitive to state-of-the-art quartz crystal-based transmitters as well as to already existing crystal-less architectures.

On the Mechanisms Governing Spurious Tone Injection in Fractional PLLs

In fractional phase-locked loop driven by ${\Sigma \Delta }$ modulators there can be spurious tones in the power spectral density (PSD) of output signals even if the PSDs of the sequences used to drive the frequency divider are spur-free. This is due to undesirable nonlinear effects notably occurring in the charge pump (CP). In this brief, we focus on static and dynamic mismatch of the CP and its interaction with the digital delay usually present in the reset path of the phase-frequency detector. Despite the presence of nonlinearities, we show that spurs may not appear, and mechanisms governing their existence are unveiled. A compact and simple model is presented allowing the onset of spurs and their magnitude to be reliably estimated.

Parametric Analysis of a Novel Architecture of Phase Locked Loop for Communication System

The work proposed parametric analysis of a novel architecture of phase locked loop (PLL) for pure signal synthesis. It has been widely used in wireless communication systems due to the high frequency resolution and the short locking time. First, we presented a mathematical and accurate model of noise in PLL with take into account noise of its component. Then we predicted output phase noise in term of its parameters. Finally, we described as effective technique for noise in fractional PLL by CppSim simulator. The output phase noise has been reduced from $$-154$$ - 154 to $$-159\,$$ - 159 dBc/MHz at 20 MHz offset. The proposed behavioral simulation results show improvement around 5 dBc/MHz. In future, this technique can also be implemented in hybrid PLL.

Fractional-N PLL based FMCW sweep generator for an 80 GHz radar system with 24.5 GHz bandwidth

Abstract. A phase-locked loop (PLL) based frequency synthesizer capable of generating highly linear broadband frequency sweeps as signal source of a high resolution 80 GHz FMCW radar system is presented. The system achieves a wide output range of 24.5 GHz starting from 68 GHz up to 92.5 GHz. High frequencies allow the use of small antennas for small antenna beam angles. The wide bandwidth results in a radar system with a very high range resolution of below 1.5 cm. Furthermore, the presented synthesizer provides a very low phase noise performance of −80 dBc/Hz at 80 GHz carrier frequency and 10 kHz offset, which enables high precision distance measurements with low range errors. This is achieved by using two nested phase-looked loops with high order loop filters. The use of a fractional PLL divider and a high phase frequency discriminator (PFD) frequency assures an excellent ramp linearity.

Hybrid Dual-Mode Frequency Synthesis for Cognitive Multi-radio Front-Ends

This paper investigates a novel approach to reconfigurable frequency synthesis for flexible radio transceivers in future cognitive multi-radios. The frequency range covered by the proposed multi-radio synthesizer corresponds to the frequency bands of the most diffused wireless communication standards operating in the radio band ranging from 800 MHz to 6 GHz. A hybrid phase locked loop (PLL) based frequency synthesizer is proposed here and a novel switching protocol is presented and validated on an experimental evaluation board. The proposed architecture combines fractional and integer PLL modes of operation along with a switched loop filter topology. Compared to standard PLL techniques, the proposed configuration provides great flexibility options and moreover, it offers relatively low circuit complexity and low power consumption. The proposed architecture provides reconfigurability of the loop bandwidth, frequency resolution, phase noise and settling time performance and hence, it can adapt itself to diverse requirements given by the concerned wireless communication standards.

A 3.2-GHz Down-Spread Spectrum Clock Generator Using a Nested Fractional Topology

A high-speed triangular-modulated spread-spectrum clock generator using a fractional phase-locked loop is presented. The fractional division is implemented by a nested fractional topology, which is constructed from a dual-modulus divide-by-(N–1/16)/N divider to divide the VCO outputs as a first division period and a fractional control circuit to establish a second division period to cause the overall fractional division. The dual-modulus divider introduces a delay-locked-loop network to achieve phase compensation. Operating at the frequency of 3.2 GHz, the measured peak power reduction is around 16 dB for a deviation of 0.37% and a frequency modulation of 33 kHz. The circuit occupies 1.4 × 1.4 mm2 in a 0.18-μm CMOS process and consumes 52 mW.

A DDS-based PLL for 2.4-GHz frequency synthesis

In this transactions brief, we present a direct digital synthesizer (DDS)-based phase-locked loop (PLL), for frequency synthesis at 2.4 GHz with 80-MHz tuning range. The DDS signal is mixed with the voltage-control oscillator output in the PLL feedback path. This solution helps in avoiding some of the typical tradeoffs in PLL. In particular, it is possible to achieve a very high-frequency resolution together with fast settling and spectral purity. These characteristics are often incompatible both in integer and fractional dividers PLL. A prototype was fabricated on PCBs and tested. The settling time is about 3 /spl mu/s for 0.1 ppm (240 Hz) accuracy. Worst-case spurs are -53 dBc at 8-MHz offset from the carrier. The integrated phase noise in the band 1 kHz -1 MHz is 0.9/spl deg/ rms. This architecture is also suitable for direct frequency modulation, without necessitating any calibration system.

Design of a fractional phase locked-loop frequency synthesiser using a Motorola based microcontroller

A Motorola M58HC11EVB board [1] is used in the design of a frequency synthesiser using a fractional phase-locked loop technique which synthesises frequencies that are integer plus fractional times higher than the reference frequency. The method uses a 68HC11 microprocessor to generate very stable reference frequencies [1]. A software program is designed to give great flexibility in selecting the reference over a desired operating range of frequencies. The ability to operate at low reference frequencies (≈10 Hz) enables the system to step in 1 Hz increments. A frequency synthesiser over the bands of 10–150 Hz, 100–1500 Hz, 1–15 kHz, and 10–150 kHz in steps of ±1 Hz, ±10 Hz, ±100 Hz and ± 1 kHz, respectively, is accomplished. The spectrum purity of the waveform for different frequencies is measured. Sideband frequencies of up to 50 dB below the synthesised frequency are observed.