Parametric Analysis of a Novel Architecture of Phase Locked Loop for Communication System

Abstract

The work proposed parametric analysis of a novel architecture of phase locked loop (PLL) for pure signal synthesis. It has been widely used in wireless communication systems due to the high frequency resolution and the short locking time. First, we presented a mathematical and accurate model of noise in PLL with take into account noise of its component. Then we predicted output phase noise in term of its parameters. Finally, we described as effective technique for noise in fractional PLL by CppSim simulator. The output phase noise has been reduced from $$-154$$ - 154 to $$-159\,$$ - 159 dBc/MHz at 20 MHz offset. The proposed behavioral simulation results show improvement around 5 dBc/MHz. In future, this technique can also be implemented in hybrid PLL.