Low jitter hybrid Phase Locked Loop

R Prithivi Raj,S Senthilnathan,S Balaji,K S Srinivasan

doi:10.1109/eait.2012.6408017

Low jitter hybrid Phase Locked Loop

R Prithivi Raj, S Senthilnathan + Show 2 more

https://doi.org/10.1109/eait.2012.6408017

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Publication Date: Nov 1, 2012

Affiliation: Anna University, Chennai

#Hybrid Phase Locked Loop #Phase Locked Loop + Show 8 more

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Abstract

In this paper, we present Low jitter hybrid Phase Locked Loop (PLL). PLL are widely used in digital communication receivers because they generate a necessary clock signal, the PLLs used in communication receivers require to generate a low-jitter clock with fast frequency and phase lock. Our hybrid PLL (HPLL) architecture consists of a LC-PLL followed by a Ring-PLL. The HPLL achieves improved jitter performance with a wide frequency range. The Ring PLL noise performance is improved using an LCPLL as a reference clock generator.

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