A 250 MHz low jitter adaptive bandwidth PLL

Abstract

Phase-locked loops (PLL) are widely used for clock recovery in digital communication receivers because they generate a necessary clock signal with relatively low hardware cost. The PLLs used in receivers are usually required to generate a low-jitter clock, but at the same time, to achieve fast frequency and phase lock. Conventional analog PLLs can generate a low-jitter clock signal with a narrow loop bandwidth, at the expense of lengthened locking time. As an alternative, a digital PLL or a hybrid analog/digital PLL can achieve a 50-cycle lock with a 125 ps jitter from an unknown frequency. But, its inherent complexity causes problems such as a large die, low speed, and high power consumption. A sophisticated loop bandwidth control algorithm is applied such as a gear-shifting or a lock-detection algorithm to the conventional analog PLLs. Here, the PLLs dynamically control the loop bandwidth by changing the charge-pump current in real time according to a well-designed current control sequence stored in its memory. However, in many applications such as high-speed HDDs and DVDs under the influence of phase fluctuation, instant frequency shift, and varying jitter, the stored fixed sequence in its memory is not adequate. This gear-shifting PLL achieves fast locking with low jitter in a time-varying channel.