FPGA Vendors Research Articles

Towards development of an analytical model relating FPGA architecture parameters to routability

We present an analytical model relating FPGA architectural parameters to the routability of the FPGA. The inputs to the model include the channel width and the connection and the switch block flexibilities. The output is an estimate of the proportion of nets in a large circuit that can be expected to be successfully routed on the FPGA. We assume that the circuit is routed to the FPGA using a single-step combined global/detailed router. We show that the model correctly predicts routability trends. We also present an example application to demonstrate that this model may be a valuable tool for FPGA architects. When combined with the earlier works on analytical modeling, our model can be used to quickly predict the routability without going through any stage of an expensive CAD flow. We envisage that this model will benefit FPGA architecture designers and vendors to quickly evaluate FPGA routing fabrics.

BioThreads: A Novel VLIW-Based Chip Multiprocessor for Accelerating Biomedical Image Processing Applications

We discuss BioThreads, a novel, configurable, extensible system-on-chip multiprocessor and its use in accelerating biomedical signal processing applications such as imaging photoplethysmography (IPPG). BioThreads is derived from the LE1 open-source VLIW chip multiprocessor and efficiently handles instruction, data and thread-level parallelism. In addition, it supports a novel mechanism for the dynamic creation, and allocation of software threads to uncommitted processor cores by implementing key POSIX Threads primitives directly in hardware, as custom instructions. In this study, the BioThreads core is used to accelerate the calculation of the oxygen saturation map of living tissue in an experimental setup consisting of a high speed image acquisition system, connected to an FPGA board and to a host system. Results demonstrate near-linear acceleration of the core kernels of the target blood perfusion assessment with increasing number of hardware threads. The BioThreads processor was implemented on both standard-cell and FPGA technologies; in the first case and for an issue width of two, full real-time performance is achieved with 4 cores whereas on a mid-range Xilinx Virtex6 device this is achieved with 10 dual-issue cores. An 8-core LE1 VLIW FPGA prototype of the system achieved 240 times faster execution time than the scalar Microblaze processor demonstrating the scalability of the proposed solution to a state-of-the-art FPGA vendor provided soft CPU core.

Slotless module-based reconfiguration of embedded FPGAs

The difficult aspect of hardware reconfiguration is not creating the computational blocks, which are generally available from FPGA vendors and third parties, but linking the blocks in a manner that suits each application's unique connectivity, bandwidth, and latency requirements. Our approach uses the standard Xilinx implementation tools to generate dynamic module partial bitstreams, but choosing the module's coordinates and completing connections to other modules are runtime operations. Scripts automatically add interface wrappers to dynamic modules and generate a library of relocatable partial bitstreams. The library is used by an efficient runtime system that completes application requests for instancing and connecting modules, effectively insulating the designer from FPGA reconfiguration complexities. In this way, a large sandbox may be allocated to dynamic modules rather than fixed module slots and interconnect. Application engineers interact with the Wires on Demand (WoD) system through a runtime software API, and do not have to master hardware description languages and implementation tools.

Teaching Hardware Description Languages to Satisfy Industry Expectations

Industry demands that computer engineers have expertise in FPGA prototyping. A broad knowledge of a hardware description language (HDL) such as Verilog or VHDL is no longer sufficient. Industry expects engineers to write RTL-synthesizable code. Unfortunately, many colleges do not teach this material because the HDL is taught as a secondary topic in a digital design course. That approach does not allow sufficient time to cover efficient coding practices, the use of third-party IP and other essential topics. This paper describes an FPGA prototyping course, based on the Verilog HDL, that is completely separate from any digital design course. The prototyping course is supplemented with FPGA vendor application notes, uses industry-standard EDA tools and fully meets industry expectations.

Design and implementation of a MicroBlaze-based warp processor

While soft processor cores provided by FPGA vendors offer designers with increased flexibility, such processors typically incur penalties in performance and energy consumption compared to hard processor core alternatives. The recently developed technology of warp processing can help reduce those penalties. Warp processing is the dynamic and transparent transformation of critical software regions from microprocessor execution to much faster circuit execution on an FPGA. In this article, we describe an implementation of a warp processor on a Xilinx Virtex-II Pro and Spartan3 FPGAs incorporating one or more MicroBlaze soft processor cores. We further provide a detailed analysis of the energy overhead of dynamically partitioning an application's kernels to hardware executing within an FPGA. Considering an implementation that periodically partitions the executing application once every minute, a MicroBlaze-based warp processor implemented on a Spartan3 FPGA achieves average speedups of 5.8× and energy reductions of 49% compared to the MicroBlaze soft processor core alone—providing competitive performance and energy consumption compared to existing hard processor cores.

Fonctions élémentaires en virgule flottante pour les accélérateurs reconfigurables

The capacity of reconfigurable circuits nowadays allows them to tackle floating-point acceleration tasks. Operators for the basic operations have been described in the literature and are now available from FPGA vendors. The next step is to provide operators for the main elementary functions. This article presents operator architectures for exponential, logarithm, sine and cosine, and studies the tradeoffs involved. For each of these functions, one of these operators has ten times the throughput of a general-purpose processor, while consuming a small fraction of the FPGA resources. These operators are freely available at http://www.ens-lyon.fr/LIP/Arenaire/.

Simplified Hardware Bit Correlator

This letter proposes a suboptimal implementation of a binary correlator suitable for detecting a known fixed pattern in a binary stream. The theoretical performances in terms of the probability of nondetection and the probability of false alarm are evaluated. These performances show that the degradations are negligible. Compared to a proprietary core provided by FPGA vendor, this implementation allows a 15 % look-up table reduction, a 30 % register reduction and up to a 30 % higher clock frequency in a FPGA.

Is there really such a thing as a "DSP" anymore?

The use of a traditional signal processing device like a digital signal processor (DSP) has been limited to lower-volume complex wireless systems, as higher-volume wireless products tend to use more integrated programmable system on a chip technologies. The emergence of multicore devices combining the functionality of ASSPs, GPPs, DSPs, and FPGAs into a single offering complicates the design choices in radio systems. The development team for any new advanced wireless product must now spend considerable effort evaluating whether a radio function traditionally performed on an ASIC would be better implemented differently. Design choices are expected to become even more difficult as the competition tighten between DSP and FPGA vendors in the various segments of the wireless markets

Synthèse automatique de microcontrôleurs spécialisés sur FPGA

In this paper we present an automated flow geared toward the synthesis of application specific micro-controllers for FPG As, targeted at control dominated applications. Our flow takes as input an application described in C, and uses profiling information to extract a specialized instruction set. This instruction set is then mapped to a generic RISC micro-architecture model, for which we generate a synthesizable VHDL description, along with its associated program. The flow has been validated on a set of representative applications and our preliminary experimental results show that our generated architectures are very competitive with FPGA vendor specific processor soft-cores, in terms of code size, resource usage and performance.

HIDE: A hardware intelligent description environment

This paper presents a logic-based structural hardware design environment, called HIDE, developed at the Queen’s University of Belfast. Central to this environment is a hardware description language which provides more abstract and elegant hardware descriptions and compositions than are possible in traditional hardware description languages such as VHDL or Verilog. The guiding principle in designing HIDE was the satisfaction of the dual requirement of abstract hardware design and hardware efficiency. The paper presents several novel developments of earlier published work, including the detailed syntax, semantic and implementation of the latest version of HIDE. The latter includes 3D circuit composition, layout managers and higher level block constructors. Using a small set of powerful constructors, HIDE allows hardware designers to describe and assemble highly efficient circuits from high level geometrical descriptions based on Signal Flow Graphs (SFG). Optimised hardware is generated automatically from such descriptions in the form of fully placed configurations in EDIF format, or VHDL. The paper illustrates this in the construction of a high performance Matrix-Multiplier core for Xilinx Virtex FPGAs. Comparative implementation results are presented which show that our HIDE system matches the performance (in terms of speed and area) of specialised FPGA vendor tools such as the Xilinx core generator, with the added feature of being a full programming environment. A qualitative comparison of the HIDE language with other hardware design languages, namely: the industry standard VHDL and a hardware design language similar to HIDE, called LAVA, shows several merits of HIDE and outlines future development plans.

Dynamic clock-frequencies for FPGAs

Most FPGA designs run at a fixed clock-frequency determined through static analysis in FPGA vendor supplied tools. Such a clocking strategy cannot take advantage of the full run-time potential of an application running on a specific device and in a specific operating environment. This paper describes methods for using dynamic clock-frequencies to overcome this limitation. We begin by describing a methodology for designing systems which allow dynamic clock-frequencies in FPGAs. We then present a framework for exploring the dynamic behaviour of suitable clock-frequencies for a number of FPGA applications in varied operational environments. Finally we introduce our AutoTEA system, which automatically adds circuitry to arbitrary FPGA designs for dynamically adjusting clock-frequency to a safe limit given current operating conditions. Our results show that dynamically clocking designs can lead to a speed improvement of 33–86% compared to using a fixed, statically estimated clock.

INSTANCE-SPECIFIC SOLUTIONS FOR ACCELERATING THE CKY PARSING OF LARGE CONTEXT-FREE GRAMMARS

The main contribution of this paper is an FPGA-based implementation of an instance-specific hardware which accelerates the CKY (Cocke-Kasami- Younger) parsing of context-free grammars. Given a context-free grammar G and a string x, the CKY parsing determines whether G derives x. We developed a hardware generator that creates a Verilog HDL source to perform the CKY parsing for any fixed context-free grammar G. The generated source is embedded in an FPGA using the design software provided by the FPGA vendor. The results show that our instance-specific hardware solution attains an astonishing speed-up factor of up to 3,700 over traditional software solutions.

FPGAs achieve superior speed and density with antifuse advancements

FPGAs based on low-resistance, low-capacitance “antifuse” programmable elements offer very high-speed performance with small, cost-effective die sizes for high-volume production applications. FPGA vendors continue to invest in this technology to push further into the performance and density/cost realm previously dominated by conventional mask programmed ASICs. These high-performance, high-density antifuse based products will further distance themselves in speed, cost, and ease-of-use from slower, more costly RAM-based FPGAs.