Abstract
In this paper we present an automated flow geared toward the synthesis of application specific micro-controllers for FPG As, targeted at control dominated applications. Our flow takes as input an application described in C, and uses profiling information to extract a specialized instruction set. This instruction set is then mapped to a generic RISC micro-architecture model, for which we generate a synthesizable VHDL description, along with its associated program. The flow has been validated on a set of representative applications and our preliminary experimental results show that our generated architectures are very competitive with FPGA vendor specific processor soft-cores, in terms of code size, resource usage and performance.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
