FPGA Platform Research Articles

Configurable Mixed-Radix Number Theoretic Transform Architecture for Lattice-Based Cryptography

Lattice-based cryptography continues to dominate in the second-round finalists of the National Institute of Standards and Technology post-quantum cryptography standardization process. Computational efficiency is primarily considered to evaluate promising candidates for final round selection. In lattice-based cryptosystems, polynomial multiplication is the most expensive computation and critical to improve the performance. This paper proposes an efficient number theoretic transform (NTT) architecture to accelerate the polynomial multiplication. The proposed design applies mixed-radix multi-path delay feedback architecture and flexibly adopts various polynomial sizes. Configurable NTT design is realized to perform forward and inverse NTT computations on a unified hardware, which is then used to develop an efficient polynomial multiplier. The proposed architectures were successfully accelerated on several Xilinx FPGA platforms to directly compare with state-of-the-art works. The implementation results show that the proposed NTT architectures have comparable area-time product and demonstrate <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.7\sim 17\times $ </tex-math></inline-formula> performance improvement, and the proposed polynomial multipliers achieve higher performance compared with previous works. Experimental results confirmed the proposed design’s applicability for high-speed large-scale data cryptoprocessors.

An Efficient and Reliable Chaos-Based IoT Security Core for UDP/IP Wireless Communication

The ultimate focus of this paper is to provide a hyperchaos-based reconfigurable platform for the real-time securing of communicating embedded systems interconnected in networks according to the Internet of Things (IoT) standards. The proposed platform’s Register Transfer Level (RTL) architecture is entirely developed and designed from scratch using the VHSIC Hardware Description Language (VHDL). The original idea consists of exploiting the nonlinearity of a discretized and optimized 4D Lorenz hyperchaotic system as an encryption keystream generator in a symmetric cryptosystem to secure wireless communicating embedded systems and adapted to the UDP/IP protocol. It was necessary to go through three essential steps to achieve this goal. First, a lightweight and energy-efficient hyperchaos-based encryption IP core is designed, implemented on an FPGA circuit and dedicated to IoT device security, denoted Hyperchaotic-based IoT Device Security Core (HC-IoT-DSC). The designed encryption IP core combines three subsystems: a multiple key size hyperchaotic key generator (HC-KG), a hyperchaotic synchronization by dynamic feedback modulation technique (HCS-DFM), and an online FIPS 140-2-based built-in self-security test (BISST) module. Second, a secure UDP/IP stack is totally implemented using the VHDL language. Third, the proposed architecture was integrated into real-world and real-time secure wireless communication at a distance of 2 km between two delocalized network nodes employing the Xilinx ML605 FPGA platform and the ZigBee E800-DTU module. A panoply of online/offline investigations and experiments were carried out intensely, deeply, and thoroughly to analyze, evaluate and validate the robustness and security aspects of the proposed scheme regarding all the aspects related to embedded system security. Notably, the evaluations were conducted in two phases for all the platform components before and after integrating the proposed security core in real-time wireless communication. The investigations and implementation findings validate that the proposed architecture can attain good performances, and confirm the feasibility of the adopted approach for IoT applications. Furthermore, the timing and power efficiency results present an excellent trade-off between design performance and high-security achievement.

ReAAP: A Reconfigurable and Algorithm-Oriented Array Processor with Compiler-Architecture Co-Design

Parallelism and data reuse are the most critical issues for the design of hardware acceleration in a deep learning processor. Besides, abundant on-chip memories and precise data management are intrinsic design requirements because most of deep learning algorithms are data-driven and memory-bound. In this paper, we propose a compiler-architecture co-design scheme targeting a reconfigurable and algorithm-oriented array processor, named ReAAP. Given specific deep neural networks, the proposed co-design scheme is effective to perform parallelism and data reuse optimization on compute-intensive layers for guiding reconfigurable computing in hardware. Especially, the systemic optimization is performed in our proposed domain-specific compiler to deal with the intrinsic tensions between parallelism and data locality, for the purpose of automatically mapping diverse layer-level workloads onto our proposed reconfigurable array architecture. In this architecture, abundant on-chip memories are software-controlled and its massive data access is precisely handled by compiler-generated instructions. In our experiments, the ReAAP is implemented on an embedded FPGA platform. Experimental results demonstrate that our proposed co-design scheme is effective to integrate software flexibility with hardware parallelism for accelerating diverse deep learning workloads. As a whole system, ReAAP achieves a consistently high utilization of hardware resource for accelerating all the diverse compute-intensive layers in ResNet, MobileNet, and BERT.

Visual Perceptual Quality Assessment Based on Blind Machine Learning Techniques.

This paper presents the construction of a new objective method for estimation of visual perceiving quality. The proposal provides an assessment of image quality without the need for a reference image or a specific distortion assumption. Two main processes have been used to build our models: The first one uses deep learning with a convolutional neural network process, without any preprocessing. The second objective visual quality is computed by pooling several image features extracted from different concepts: the natural scene statistic in the spatial domain, the gradient magnitude, the Laplacian of Gaussian, as well as the spectral and spatial entropies. The features extracted from the image file are used as the input of machine learning techniques to build the models that are used to estimate the visual quality level of any image. For the machine learning training phase, two main processes are proposed: The first proposed process consists of a direct learning using all the selected features in only one training phase, named direct learning blind visual quality assessment . The second process is an indirect learning and consists of two training phases, named indirect learning blind visual quality assessment . This second process includes an additional phase of construction of intermediary metrics used for the construction of the prediction model. The produced models are evaluated on many benchmarks image databases as , , and in the wild image quality challenge. The experimental results demonstrate that the proposed models produce the best visual perception quality prediction, compared to the state-of-the-art models. The proposed models have been implemented on an platform to demonstrate the feasibility of integrating the proposed solution on an image sensor.

To the question of realization of machine vision technology based on FPGA-architectures

In the last few years, machine learning and machine vision technologies have started to gain more and more popularity. This industry occupies one of the leading positions in the field of information technology. The paper is devoted to the development of a machine vision algorithm based on new generations of FPGAs for recognizing handwritten Cyrillic characters in images and video streams, in particular. The article raises the issues of using FPGA as an image segmentation accelerator and organizing work with the video stream, choosing the most suitable FPGA platform, creating training samples of handwritten characters, and working with the convolutional neural network AlexNet.

The Strong Scaling Advantage of FPGAs in HPC for N-body Simulations

N-body methods are one of the essential algorithmic building blocks of high-performance and parallel computing. Previous research has shown promising performance for implementing n-body simulations with pairwise force calculations on FPGAs. However, to avoid challenges with accumulation and memory access patterns, the presented designs calculate each pair of forces twice, along with both force sums of the involved particles. Also, they require large problem instances with hundreds of thousands of particles to reach their respective peak performance, limiting the applicability for strong scaling scenarios. This work addresses both issues by presenting a novel FPGA design that uses each calculated force twice and overlaps data transfers and computations in a way that allows to reach peak performance even for small problem instances, outperforming previous single precision results even in double precision, and scaling linearly over multiple interconnected FPGAs. For a comparison across architectures, we provide an equally optimized CPU reference, which for large problems actually achieves higher peak performance per device, however, given the strong scaling advantages of the FPGA design, in parallel setups with few thousand particles per device, the FPGA platform achieves highest performance and power efficiency.

CFNTT: Scalable Radix-2/4 NTT Multiplication Architecture with an Efficient Conflict-free Memory Mapping Scheme

Number theoretic transform (NTT) is widely utilized to speed up polynomial multiplication, which is the critical computation bottleneck in a lot of cryptographic algorithms like lattice-based post-quantum cryptography (PQC) and homomorphic encryption (HE). One of the tendency for NTT hardware architecture is to support diverse security parameters and meet resource constraints on different computing platforms. Thus flexibility and Area-Time Product (ATP) become two crucial metrics in NTT hardware design. The flexibility of NTT in terms of different vector sizes and moduli can be obtained directly. Whereas the varying strides in memory access of in-place NTT render the design for different radix and number of parallel butterfly units a tough problem. This paper proposes an efficient conflict-free memory mapping scheme that supports the configuration for both multiple parallel butterfly units and arbitrary radix of NTT. Compared to other approaches, this scheme owns broader applicability and facilitates the parallelization of non-radix-2 NTT hardware design. Based on this scheme, we propose a scalable radix-2 and radix-4 NTT multiplication architecture by algorithm-hardware co-design. A dedicated schedule method is leveraged to reduce the number of modular additions/subtractions and modular multiplications in radix-4 butterfly unit by 20% and 33%, respectively. To avoid the bit-reversed cost and save memory footprint in arbitrary radix NTT/INTT, we put forward a general method by rearranging the loop structure and reusing the twiddle factors. The hardware-level optimization is achieved by excavating the symmetric operators in radix-4 butterfly unit, which saves almost 50% hardware resources compared to a straightforward implementation. Through experimental results and theoretical analysis, we point out that the radix-4 NTT with the same number of parallel butterfly units outperforms the radix-2 NTT in terms of area-time performance in the interleaved memory system. This advantage is enlarged when increasing the number of parallel butterfly units. For example, when processing 1024 14-bit points NTT with 8 parallel butterfly units, the ATP of LUT/FF/DSP/BRAM n radix-4 NTT core is approximately 2.2 × /1.2 × /1.1 × /1.9 × less than that of the radix-2 NTT core on a similar FPGA platform.

Composite Enclaves: Towards Disaggregated Trusted Execution

The ever-rising computation demand is forcing the move from the CPU to heterogeneous specialized hardware, which is readily available across modern datacenters through disaggregated infrastructure. On the other hand, trusted execution environments (TEEs), one of the most promising recent developments in hardware security, can only protect code confined in the CPU, limiting TEEs’ potential and applicability to a handful of applications. We observe that the TEEs’ hardware trusted computing base (TCB) is fixed at design time, which in practice leads to using untrusted software to employ peripherals in TEEs. Based on this observation, we propose composite enclaves with a configurable hardware and software TCB, allowing enclaves access to multiple computing and IO resources. Finally, we present two case studies of composite enclaves: i) an FPGA platform based on RISC-V Keystone connected to emulated peripherals and sensors, and ii) a large-scale accelerator. These case studies showcase a flexible but small TCB (2.5 KLoC for IO peripherals and drivers), with a low-performance overhead (only around 220 additional cycles for a context switch), thus demonstrating the feasibility of our approach and showing that it can work with a wide range of specialized hardware.

Radix‐16 CSA‐based low‐latency non‐Montgomery modular multiplier

The long-precision modular multiplier is usually performed by Montgomery algorithm with bit shifts, yielding a result in the form of A · B · 2 − n mod M . In fact, with the precomputation of δ · 2 n mod M proposed by others, it is able to compute classic modular multiplication A · B mod M rather than Montgomery modular multiplication A · B · N − 1 mod M . In this work, a multi-bit CSA-based long-precision modular multiplier is proposed for hardware implementation. It includes two carry save adders and one RAM access to perform modular multiplications. After every modular multiplication, a division is applied to reduce the result down to [ 0 , M ) . Hardware implementation results show that a 1024-bit modular multiplication can be completed in 2.39 μs on the XC5V FPGA platform, costing 5793 slices, 8 DSPs and 36 BRAMs, which is a promising candidate to compute incontinuous classic modular multiplications.

Sub-nanosecond synchronization implementation in pure Xilinx Kintex-7 FPGA

White Rabbit (WR) provides high-performance synchronization with sub-nanosecond accuracy and picoseconds precision, and it has been included in the new High Accuracy Default PTP Profile in the IEEE 1588-2019. As an open-source project, WR Precision Time Protocol (WR-PTP) core has been implemented in different FPGA platforms with dedicated clock circuits. This paper presents a novel approach to achieve the WR function in Xilinx Kintex-7 FPGA depending on the on-chip resource. This approach could achieve sub-nanosecond accuracy and tens of picoseconds precision, simplifying WR devices' hardware design and making it possible to port the WR PTP core to many mature hardware platforms.

Area-Delay-Power Efficient VLSI Architecture of FIR Filter for Processing Seismic Signal

Low-complexity, high-speed and re-configurability are the primary requirements of the finite impulse response (FIR) filters employed for the processing of acquired seismic signal in real-time seismic-alert-system. The common sub-expression elimination (CSE) technique is employed widely to reduce the hardware complexity by minimizing the logic operators (LOs) and logic depths (LDs) in digital FIR filter. In this brief, a novel matrix grouped CSE (MCSE) algorithm has been proposed which outperforms the existing CSE algorithms in terms of LOs and LDs minimization. Moreover, a new half-unit biased (HUB) based rounding technique is incorporated in the proposed design to reduce the truncation error while maintaining low-complexity and the cut-set retiming technique is employed to reduce the critical-path-delay (CPD). Two hardware efficient FIR filter architectures (I and II) involving the proposed canonical signed digit (CSD) based MCSE algorithm, HUB rounding and cut-set retiming approach have been presented. Further, the architecture II represents a hardware efficient realization of a reconfigurable FIR filter. The hardware implementation of the architectures is performed on both FPGA and ASIC platforms. The hardware implementation of the proposed architecture I yields more than 25%, 49%, 38%, 36% and, 31% reduction in LOs, CPD, effective latency, area-delay-product (ADP) and, power-delay-product (PDP), respectively, over the state-of-the-art CSE based architectures. Whereas the reconfigurable architecture II exhibits nearly 48%, 12% and, 13% reduction in CPD, ADP and, PDP over the counterpart.

Analysis of Efficient Implementation of Elliptic Curve Cryptography Architecture for Resource Constraint Application

Elliptic Curve Cryptography is gaining attraction in providing a high security level in data transmission with low cost, small key size and smaller hardware realization. High-speed implementation is a significant factor in ECC applications such as smart cards, network servers, wireless sensor based networks, Internet of Things and Radio Frequency Identification. These applications require low-cost and lightweight implementations. In the resource constrain application, lightweight cryptography has emerged as the desired one because of limited energy in devices and the scarce computational resources. Design options and a wide range of parameters affect the overall implementation of the ECC system. Implementation target device, coordinate system, underlying finite fields and modular arithmetic algorithms are key design parameters that impact the overall implementation outcome. A statistical study is conducted on a large collection of published work based on the design parameters. The basic question that arises is how to select the appropriate flexibility-efficiency tradeoff. The subjects of generator, versatile, reconfigurable, dedicated and general purpose scalar multipliers are addressed. A review of various algorithms to perform scalar multiplication on prime and binary fields has been done more effectively. The results of ECC implementation on different FPGA platform is compared and analyzed with the various performance parameters. Besides, a classification of the previous works in terms of flexibility, performance, scalability and cost effectiveness is presented.

Routing Density Analysis of Area-Efficient Ring Oscillator Physically Unclonable Functions

The research into ring oscillator physically unclonable functions (RO-PUF) continues to expand due to its simple structure, ease of generating responses, and its promises of primitive security. However, a substantial study has yet to be carried out in developing designs of the FPGA-based RO-PUF, which effectively balances performance and area efficiency. This work proposes a modified RO-PUF where the ring oscillators are connected directly to the counters. The proposed RO-PUF requires fewer RO than the conventional structure since this work utilizes the direct pulse count method. This work aims to seek the ideal routing density of ROs to improve uniqueness. For this purpose, five logic arrangements of a wide range of routing densities of ROs were tested. Upon implementation onto the FPGA chip, the routing density of ROs are varied significantly in terms of wire utilization (higher than 25%) and routing hotspots (higher than 80%). The best uniqueness attained was 52.71%, while the highest reliability was 99.51%. This study improves the uniqueness by 2% subsequent to the application of scenarios to consider ROs with a narrow range of routing density. The best range of wire utilization and routing hotspots of individual RO in this work is 3–5% and 20–50%, respectively. The performance metrics (uniqueness and reliability) of the proposed RO-PUF are much better than existing works using a similar FPGA platform (Altera), and it is as good as the recent RO-PUFs realized on Xilinx. Additionally, this work estimates the minimum runtimes to reduce error and response bit-flip of RO-PUF.

Revisiting the ECM-KEEM protocol with Vedic multiplier for enhanced speed on FPGA platforms

Revisiting the ECM-KEEM protocol with Vedic multiplier for enhanced speed on FPGA platforms

The Cost of a True Random Bit—On the Electronic Cost Gain of ASIC Time-Domain-Based TRNGs

Random number generators are of paramount importance in numerous fields. Under certain well-defined adversarial settings, True Random Number Generators (TRNGs) are more secure than their computational (pseudo) random number generator counterparts. TRNGs are also known to be more efficiently implemented on hardware platforms where, for various applications, efficiency in terms of electronic cost factors is critical. In this manuscript, we first provide an evaluation of robustness and reliability of efficient time-domain-based TRNG implementation over FPGA platform. In particular, we demonstrate sensitivities which imply a TRNG construction which is not agnostic to electronic-design-automation tools and to the level of designers’ know-how. This entails a large amount of effort and validation to make the designs robust, as well as requires a high degree of complexity from non-trivial FPGAs flows. This motivates the second part of the manuscript, where we propose an ASIC-based implementation of the TRNG, along with the optimization steps to enhance its characteristics. The optimized design improves the randomness-throughput by 42× for the same entropy level described in previous works, and it can provide maximal entropy level of 0.985 with 7× improvement in randomness throughput over the raw samples (no pre-processing). The proposed design simultaneously provides a reduced energy of 0.1 (mW/bit) for the same entropy level as previous works, and 1.06 (mW/bit) for the higher entropy flavor, and a lower area utilization of 0.000252 (mm2) on a 65 nm technology evaluation, situating it in the top-class of the discuss ratings. This leads to the quantitative question of the gain in electronic cost factors over ASIC TRNGs, and the minimum Cost Per Bit/Source possible to date. Finally, we exemplify a TRNG versus PRNG cost-extrapolation for security architects and designers, targeting an ASIC scenario feeding a lightweight encryption core.

Designing SPI to I2C Protocol Converter Base on ASIC Technology and Implementing on the FPGA Platform

Nowadays embedded systems are using a lot of different communication standards to transfer data such as USB, UART, SPI, I2C, etc. To be able to transfer data with each communication standard, the system needs at least one controller block for that communication standard. This has added to the complexity of the system and the cost of manufacturing hardware. Embedded systems only support SPI communication if desired, which can still be communicated with peripherals with I2C standard. However, the SPI cannot be directly connected to the I2C but must use a standard communication converter. This paper will primarily focus on designing an IP core communication standard converter from SPI to I2C using APB (Advanced Peripheral Bus) communication as one of the AMBA (Advanced Microcontroller Bus Architecture) communication sets. In particular, APB is a bus used to communicate with peripherals that do not require fast processing speeds such as UART, SPI, I2C, etc.

Adaptive finite control set model predictive control for three-phase inverters connected to distorted grid with fewer voltage sensors

This paper proposes an adaptive finite control set model predictive control (FCS-MPC) scheme for three-phase inverters connected to distorted grid with fewer voltage sensors. For the distorted grid voltage construction, a composite observer is introduced. The observer is composed of two parts, a phase detection module and time-varying observers. The phase information is obtained by the measured voltage of one phase. Then the other two-phase grid voltage is identified by time-varying observers. The convergence of time-varying observers is guaranteed by a Lyapunov function and the Lasalle invariance principle. Moreover, the outputs of the observer are the DC component and the amplitude of each harmonic, which is helpful to obtain positive components without complex post-processing. Finally, the FCS-MPC scheme with simplified cost function is employed for current tracking in natural (abc) coordinate rather than αβ coordinate. Simulation on Matlab/Simulink and experiments on FPGA platform for the three-phase inverter under distorted grid conditions prove that the proposed control approach can perform well with fewer voltage sensors.

Efficient hardware implementation for lightweight mCrypton algorithm using FPGA

&lt;p&gt;The lightweight cryptography is used for low available resources devices such as radio frequency identification (RFID) tags, internet of things (IoTs) and wireless sensor networks. In such case, the lightweight cryptographic algorithms should consider power consumption, design area, speed, and throughput. This paper presents a new architecture of mCrypton lightweight cryptographic algorithm which considers the above-mentioned conditions. Resource-shared structure is used to reduce the area of the new architecture. The proposed architecture is implemented using ISE Xilinx V14,5 and Spartan 3 FPGA platform. The simulation results introduced that the proposed design area is 375 of slices, up to 302 MHz operating frequency, a throughput of 646 Mbps, efficiency of 1.7 Mbps/slice and 0.089 Watt power consumption. Thus, the proposed architecture outperforms similar architectures in terms of area, speed, efficiency and throughput.&lt;/p&gt;

Design of High-Speed Video Data Transmission Circuit Based on GMSL Technology

With the development of the complexity of the vehicle platform, the bandwidth required for video transmission on the vehicle platform is increasing. The traditional data bus transmission rate can no longer meet the needs in some application fields. The new generation of GMSL technology video format is equivalent to the serial interface video. Format, digital video and audio data are higher than the traditional bus data transmission rate, up to 3.12Gbps. In this context, this paper studies the design of GMSL technology high-speed video transmission circuit, completes the hardware development in ISE, uses FPGA platform to build a video video transmission control system, and completes the high-speed transmission of GMSL format video.

Estimation of frequency and phasor using enhanced nonlinear least error squares method for synchrophasor application

Nonlinear least error squares (LES) method reported in the literature, has been used for frequency estimation of power signal having harmonic contents. However, anticipation of achieving high accuracy and increased range of frequency estimate with existing solution technique leads to computational burden on FPGA processor. In this paper, a novel algorithm is proposed to enhance the accuracy of nonlinear LES technique without imposing any computational burden for the requirement of synchrophasor application. This is accomplished by finding the minimum value of squared Euclidian norm of error vector obtained by nonlinear LES method only at the selected frequency intervals. The behavior of algorithm with respect to window length of signal is analyzed through simulation. Also the proposed algorithm is employed for measurement of phasors. The performance of the proposed algorithm is verified and demonstrated for the different tests mentioned in synchrophasor standard IEEE C37.118.1 and its amendment IEEE C37.118.1a-2014. The enhanced nonlinear LES is implemented on NI cRIO 9082 using Xilinx Spartan-6 LX150 FPGA platform for real-time measurement.