Abstract
The ever-rising computation demand is forcing the move from the CPU to heterogeneous specialized hardware, which is readily available across modern datacenters through disaggregated infrastructure. On the other hand, trusted execution environments (TEEs), one of the most promising recent developments in hardware security, can only protect code confined in the CPU, limiting TEEs’ potential and applicability to a handful of applications. We observe that the TEEs’ hardware trusted computing base (TCB) is fixed at design time, which in practice leads to using untrusted software to employ peripherals in TEEs. Based on this observation, we propose composite enclaves with a configurable hardware and software TCB, allowing enclaves access to multiple computing and IO resources. Finally, we present two case studies of composite enclaves: i) an FPGA platform based on RISC-V Keystone connected to emulated peripherals and sensors, and ii) a large-scale accelerator. These case studies showcase a flexible but small TCB (2.5 KLoC for IO peripherals and drivers), with a low-performance overhead (only around 220 additional cycles for a context switch), thus demonstrating the feasibility of our approach and showing that it can work with a wide range of specialized hardware.
Highlights
For most of the computer’s history, designing an architecture around the CPU allowed extracting the most performance benefits from Moore’s law
Cloud computing architectures are even adopting a disaggregated model called composable disaggregated infrastructure (CDI) [KSP+16, LCM+09, NTT+18] in which data centers no longer consist of a number of connected servers, but of functional blocks connected with high-speed interconnects
Performance of Inter-Enclave Communication As composite enclaves supports shared memory to communicate, its communication speed is the same as what the memory bus provides. This is much faster compared to traditional trusted execution environments (TEEs), where enclaves communicate through the operating system (OS) requiring extra encryption steps
Summary
For most of the computer’s history, designing an architecture around the CPU allowed extracting the most performance benefits from Moore’s law. The demand for increased computation power is usually met with special-purpose hardware: GPUs are often orders of magnitude more efficient than a CPU for parallel workloads such as graphics and machine learning, and FPGAs often achieve similar gains for custom workloads. Some tasks such as machine learning are even pervasive enough to justify the investment into fully custom ASICs [JYP+17]. The SM maintains its own memory separate from the OS and protected by a PMP entry It facilitates all enclave calls, e.g., it creates, runs, and destroys enclaves. Keystone provides extensions for cache side-channel protections using page coloring or dynamic enclave memory
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