FPGA Design Research Articles

Near-memory Computing on FPGAs with 3D-stacked Memories: Applications, Architectures, and Optimizations

The near-memory computing (NMC) paradigm has transpired as a promising method for overcoming the memory wall challenges of future computing architectures. Modern systems integrating 3D-stacked DRAM memory can be leveraged to prevent unnecessary data movement between the main memory and the CPU. FPGA vendors have started introducing 3D memories to their products in an effort to remain competitive on bandwidth requirements of modern memory-intensive applications. Recent NMC proposals target various types of data processing workloads such as graph processing, MapReduce, sorting, machine learning, and database analytics. In this article, we conduct a literature survey on previous proposals of NMC systems on FPGAs integrated with 3D memories. By leveraging the high bandwidth offered from such memories together with specifically designed hardware, FPGA architectures have become a competitor to GPU solutions in terms of speed and energy efficiency. Various FPGA-based NMC designs have been proposed with software and hardware optimization methods to achieve high performance and energy efficiency. Our review investigates various aspects of NMC designs such as platforms, architectures, workloads, and tools. We identify the key challenges and open issues with future research directions.

Streaming Overlay Architecture for Lightweight LSTM Computation on FPGA SoCs

Long-Short Term Memory (LSTM) networks, and Recurrent Neural Networks (RNNs) in general, have demonstrated their suitability in many time series data applications, especially in Natural Language Processing (NLP) . Computationally, LSTMs introduce dependencies on previous outputs in each layer that complicate their computation and the design of custom computing architectures, compared to traditional feed-forward networks. Most neural network acceleration work has focused on optimising the core matrix-vector operations on highly capable FPGAs in server environments. Research that considers the embedded domain has often been unsuitable for streaming inference, relying heavily on batch processing to achieve high throughput. Moreover, many existing accelerator architectures have not focused on fully exploiting the underlying FPGA architecture, resulting in designs that achieve lower operating frequencies than the theoretical maximum. This paper presents a flexible overlay architecture for LSTMs on FPGA SoCs that is built around a streaming dataflow arrangement, uses DSP block capabilities directly, and is tailored to keep parameters within the architecture while moving input data serially to mitigate external memory access overheads. The architecture is designed as an overlay that can be configured to implement alternative models or update model parameters at runtime. It achieves higher operating frequency and demonstrates higher performance than other lightweight LSTM accelerators, as demonstrated in an FPGA SoC implementation.

An Optimized GIB Routing Architecture with Bent Wires for FPGA

Field-programmable gate arrays (FGPAs) are widely used because of the superiority in flexibility and lower non-recurring engineering cost. How to optimize the routing architecture is a key problem for FPGA architects because it has a large impact on FPGA area, delay, and routability. In academia, the routing architecture is mainly based on the connection blocks (CBs) and switch blocks (SBs), whereas most research has focused on SB architectures, such as Wilton, Universal, and Disjoint SB patterns. In this article, we propose a novel unidirectional routing architecture—general interconnection block (GIB)—to improve FPGA performance. With the GIB architecture, logic block (LB) pins can directly connect with the adjacent GIBs without programmable switches. Inside a GIB, LB pins can connect to the routing channel tracks on the four sides of a GIB. In particular, the logic pins from different neighboring LBs that connect to the same GIB can connect with each other with only one programmable switch. In addition, we enhance VTR to support the GIB with bent wires and develop a searching framework based on the simulated annealing algorithm to search for a near-optimal distribution of wire types. We evaluate the GIB architecture on VTR 8 with the provided benchmark circuits. The experimental results show that the GIB architecture with length-4 wires can achieve 9.5% improvement on the critical path delay and 11.1% improvement on the area-delay product compared to the VTR CB-SB architecture with length-4 wires. After exploring mixed wire types, the optimized GIB architecture can further improve the delay by 16.4% and area-delay product by 17.1% compared to the CB-SB architecture with length-4 wires.

Characteristic Analysis and Circuit Implementation of a Novel Fractional-Order Memristor-Based Clamping Voltage Drift

The ideal magnetic flux-controlled memristor was introduced into a four-dimensional chaotic system and combined with fractional calculus theory, and a novel four-dimensional commensurate fractional-order system was proposed and solved using the Adomian decomposition method. The system orders, parameters, and initial values were studied as independent variables in the bifurcation diagram and Lyapunov exponents spectrum, and it was discovered that changing these variables can cause the system to exhibit more complex and rich dynamical behaviors. The system had an offset boosting, which was discovered by adding a constant term after the decoupled linear term. Finally, the results of the numerical simulation were verified through the use of analog circuits and FPGA designs, and a control scheme for the system circuit was also suggested.

Detailed Placement for Dedicated LUT-Level FPGA Interconnect

In this work, we develop timing-driven CAD support for FPGA architectures with direct connections between LUTs. We do so by proposing an efficient ILP-based detailed placer, which moves a carefully selected subset of LUTs from their original positions, so that connections of the user circuit can be appropriately aligned with the direct connections of the FPGA, reducing the circuit’s critical path delay. We discuss various aspects of making such an approach practicable, from efficient formulation of the integer programs themselves, to appropriate selection of the movable nodes. These careful considerations enable simultaneous movement of tens of LUTs with tens of candidate positions each, in a matter of minutes. In this manner, the impact of additional connections on the critical path delay more than doubles, compared to the previously reported results that relied solely on architecture-oblivious placement.

Implementation Of Dynamically Reconfigurable NoC Using Flexible Dimension Order Routing (FDOR) Algorithm on FPGA

NoC-Based Dynamic Reconfigurable Systems (DRSs) implemented over FPGA devices change their configuration at the run time by re-positioning or replacing the existing processing modules into the network. Several Dynamically Reconfigurable NoCs (DRNoCs) in the literature, propose adaptive routing algorithms in order to handle the network structure alteration. Nevertheless, their implementation cost is severe in terms of chip area and time required to reconfigure the routing scheme, which results in non-well scalable solutions for DRSs. In this work, we propose an alternative DRNoC approach, based on a traditional 2-D mesh, using a logic-based implementation of the Flexible Direction Order Routing (FDOR) algorithm, thus inheriting its simplicity and deadlock-freedom. Several scenarios have been considered in order to prove the applicability of the FDOR algorithm in the context of a DRNoC accompanied by performance and synthesis results. In conclusion, we demonstrate that FDOR is a suitable solution for DRNoCs. This project was aimed for implementing low-cost optimized FPGA architecture. Model sim 6.5f is used for simulating the NOC and synthesized using Xilinx ISE 14.7. Then the implementation is done in Spartan3 FPGA Kit.

FPGA-Based Updatable Packet Classification Using TSS-Combined Bit-Selecting Tree

OpenFlow switches are being deployed in SDN to enable a wide spectrum of non-traditional applications. As a promising alternative to brutal force TCAMs, FPGA-based packet classification is being actively investigated. However, none of the existing FPGA designs can achieve high performance on both search and update for large-scale rule sets. To address this issue, we propose TcbTree, an FPGA-based algorithmic scheme for packet classification. Specifically, at the algorithmic side, i) a two-stage framework consisting of heterogeneous algorithms is proposed, where most rules can be mapped into several balanced trees without rule replications, ii) for the remaining few rules, a centralized TSS (Tuple Space Search) architecture together with a real-time feedback scheme is designed to enhance the efficiency of TSS search on FPGA, and iii) a tree dilution method is designed to equalize rule distribution in trees, so that the latency of tree search can be reduced. At the hardware side, i) an efficient data structure set is designed to convert tree traversal to addressing process, which breaks the constraints of limited tree depth and imbalanced node distribution, and ii) distinct from fully pipelined designs, multiple levels of parallelism are efficiently explored with multi-core, multi-search-engine and coarse-grained pipelines herein. Experimental results using ClassBench show that, with the implementation of TcbTree on FPGA, the average classification throughputs for 1k, 10k, 32k and 100k rule sets achieve 788.8 MPPS, 404.3 MPPS, 237 MPPS and 41.8 MPPS, respectively, and the update throughput for all benchmark rule sets is above 1 MUPS.

Accelerating Bayesian Neural Networks via Algorithmic and Hardware Optimizations

Bayesian neural networks (BayesNNs) have demonstrated their advantages in various safety-critical applications, such as autonomous driving or healthcare, due to their ability to capture and represent model uncertainty. However, standard BayesNNs require to be repeatedly run because of Monte Carlo sampling to quantify their uncertainty, which puts a burden on their real-world hardware performance. To address this performance issue, this article systematically exploits the extensive structured sparsity and redundant computation in BayesNNs. Different from the unstructured or structured sparsity in standard convolutional NNs, the structured sparsity of BayesNNs is introduced by Monte Carlo Dropout and its associated sampling required during uncertainty estimation and prediction, which can be exploited through both algorithmic and hardware optimizations. We first classify the observed sparsity patterns into three categories: channel sparsity, layer sparsity and sample sparsity. On the algorithmic side, a framework is proposed to automatically explore these three sparsity categories without sacrificing algorithmic performance. We demonstrated that structured sparsity can be exploited to accelerate CPU designs by up to 49 times, and GPU designs by up to 40 times. On the hardware side, a novel hardware architecture is proposed to accelerate BayesNNs, which achieves a high hardware performance using the runtime adaptable hardware engines and the intelligent skipping support. Upon implementing the proposed hardware design on an FPGA, our experiments demonstrated that the algorithm-optimized BayesNNs can achieve up to 56 times speedup when compared with unoptimized Bayesian nets. Comparing with the optimized GPU implementation, our FPGA design achieved up to 7.6 times speedup and up to 39.3 times higher energy efficiency.

TLP-LDPC: Three-Level Parallel FPGA Architecture for Fast Prototyping of LDPC Decoder Using High-Level Synthesis

TLP-LDPC: Three-Level Parallel FPGA Architecture for Fast Prototyping of LDPC Decoder Using High-Level Synthesis

Simulation research on ship electric propulsion speed regulation system based on variable structure control and FPGA

In order to improve the operating effect of the ship electric propulsion speed control system, this paper combines variable structure control and FPGA to study the ship electric propulsion speed control system, and simulates and analyzes the system. Moreover, this paper adopts a modular design and divides the FPGA design into different modules such as AD sampling control, AD data processing, logic state acquisition and control, PWM pulse generation and control, RTC control, and DTS control. In addition, this paper constructs a ship electric propulsion speed regulation system based on variable structure control and FPGA. Finally, this paper conducts simulation research on the system and counts its corresponding data. The main parameters are control reliability and speed regulation effect. According to the simulation test results, the ship electric propulsion speed control system based on variable structure control and FPGA proposed in this paper can effectively improve the propagation speed control effect.

FPGA design of arithmetic optimised APT-VDF using reusable Vedic multiplier with simplified combinational logics for medical signal denoising

ABSTRACT All-pass transformation (APT)-based variable digital filters (VDFs) can be used in different biomedical signal-processing applications, particularly in electrocardiograph denoising. In this paper, arithmetic optimised APT-VDF is proposed by modifying the hardware structure of APT-VDF based on arithmetic perception to enhance the performance in terms of area, speed and power consumption. The core blocks of the suggested Arithmetic Optimised APT-VDF (AOAPT-VDF)are adders and multipliers. This paper introduces a new reusable Vedic multiplier with redundant detection unit to identify redundant computations while generating the partial products. Also, a new Carry select adder (CSLA) with simplified combinational logics is proposed to improve the performance of the CSLA by simplifying the partial sum and carry generation logics without requiring Ripple Carry Adders. The proposed Reusable Vedic Multiplier with Redundant Detection Logic (RVM-RDL) also reuses the same vertical and cross-product generation units repetitively to reduce the area while increasing the bit length. The effectiveness of the suggested AOAPT is analysed utilising the MIT-BIH Arrhythmia Database. The proposed AOAPT-VDF consumes only 0.21 W power and achieves a 235.50 MHz operating frequency.

Energy Efficient and Low dynamic power Consumption TCAM on FPGA

Artificial Intelligence [AI] and networking applications extensively incorporate Field Programmable Gate Arrays [FPGA] - based Ternary Content Addressable Memories [TCAM]. Since FPGAs cannot support TCAMs, they must be emulated with SRAM-based memories, requiring FPGA resources. Compared to state-of-the-art designs, the proposed FPGA-based TCAM implementation will save significant resources. This methodology makes use of the Lookup Table RAMS (LUTRAMs), slice carry-chains, and flip-flops (FF) allowing simultaneous mapping of rules and deeper pipelining respectively. The TCAM implementation results in lower power consumption, lesser delays, and lower resource utilization. It outperformed conventional FPGA-based TCAMs in terms of energy efficiency (EE) and performance per area (PA) by at least 3.34 and 8.4 times respectively, and 56% better than existing FPGA designs. The proposed method outperforms all previous approaches due to its low dynamic power consumption when considering the huge size of TCAM emulation on SRAM-based FPGAs.

Proposal of a reliable embedded circuit to control a stepper motor using microblaze soft-core processor

The vast majority of embedded system designs start with a processor-based system, using a microcontroller or microprocessor as the core element to predict and process the basic control tasks. This paper aims to increase the reliability of controlling a stepper motor by an embedded circuit, which generates four digital signals of pulse width modulation (PWM). The manager of this circuit is an embedded processor licensed from Microblaze, which sits within the FPGA architecture Virtex 5. This processor analyzes the parameters to execute the rotation under the best conditions (energy consumption, speed, precision, reliability). The communication with the PC takes place via the RS232 link to provide feedback. The autonomous processor generates an independent control frequency of the PC. The four digital signals of PWM are simulated on Xilinx's ISim interface and sent to the ULN2803 amplifier circuit to run the stepper motor.

FPGA Hardware Realization of Membrane Calculation Optimization Algorithm with Great Parallelism

Aiming to investigate the disadvantage of the optimization algorithm of membrane computing (a P system) in which it is difficult to take advantage of parallelism in MATLAB, leading to a slow optimization speed, a digital-specific hardware solution (field-programmable gate array, FPGA) is proposed to design and implement the single-cell-membrane algorithm (SCA). Because the SCA achieves extensive global searches by the symmetric processing of the solution set, with independent and symmetrically distributed submembrane structures, the FPGA-hardware-based design of the SCA system includes a control module, an HSP module, an initial value module, a fitness module, a random number module, and multiple submembrane modules with symmetrical structures. This research utilizes the inherent parallel characteristics of the FPGA to achieve parallel computations of multiple submembrane modules with a symmetric structure inside the SCA, and it achieves a high degree of parallelism of rules inside the modules by using a non-blocking allocation. This study uses the benchmark Sphere function to verify the performance of the FPGA-designed SCA system. The experimental results show that, when the FPGA platform and the MATLAB platform obtain a similar calculation accuracy, the average time-consuming of the FPGA is 0.00041 s, and the average time-consuming of MATLAB is 0.0122 s, and the calculation speed is improved by nearly 40 times. This study uses the FPGA design to implement the SCA, and it verifies the advantages of the membrane-computing maximum-parallelism theory and distributed structures in computing speed. The realization platform of membrane computing is expanded, which provides a theoretical basis for further development of the distributed computing model of population cells.

An Intelligent Real-Time Object Detection System on Drones

Drones have been widely used in everyday life and they can help deal with various tasks, including photography, searching, and surveillance. Nonetheless, it is difficult for drones to perform customized online real-time object detection. In this study, we propose an intelligent real-time object detection system for drones. It is composed of an FPGA and a drone. A neural-network (NN) engine is designed on the FPGA for NN model acceleration. The FPGA receives activation data from an NN model, which are assembled into the data stream. Multiple fetch and jump pointers catch required activation values from the data stream, which are then filtered and sent to each thread independently. To accelerate processing speed, multiple processing elements (PEs) deal with tasks in parallel by using multiple weights and threads. The image data are transferred from the drone host to the FPGA, which are tackled with high speed by the NN engine. The NN engine results are returned to the host, which is used to adjust the flying route accordingly. Experimental results reveal that our proposed FPGA design well utilizes FPGA computing resources with 81.56% DSP and 72.80% LUT utilization rates, respectively. By using the Yolov3-tiny model for fast object detection, our system can detect objects at the speed of 8 frames per second and achieves a much lower power consumption compared to state-of-the-art methods. More importantly, the intelligent object detection techniques provide more pixels for the target of interest and they can increase the detection confidence score from 0.74 to 0.90 and from 0.70 to 0.84 for persons and cars, respectively.

A highly efficient FPGA implementation of AES for high throughput IoT applications

With nearly 500 billion connected devices in 2025, information security will be the main concern of the researchers. It is the driving force in developing resource efficient cryptographic solutions. In this paper, we present a high throughput AES design with 32-bit data path that achieves the high efficiency via FPGA implementation. With the help of data path compression and effective utilization of FPGA architecture, the resource consumption is minimized. Galois field arithmetic is utilized for s-box implementation. Separate S-box for key generation has been employed to achieve higher throughput and low latency. The proposed design has been synthesized by PlanAhead software and implemented on different Xilinx FPGAs. It is compared with AES implementations. With a throughput of 2.34 Gbps and efficiency of 5.10 Mbps/slice, the design outperforms different lightweight ciphers. High throughput and low latency make it suitable for surveillance applications in IoT and smart grid.

PipeNTT: A Pipelined Number Theoretic Transform Architecture

Polynomial multiplication is the key and time-consuming operation among various operators in Post-Quantum Cryptography (PQC), which aims to find quantum-resistant algorithms to prevent attacks launched by quantum computers. Number Theoretic Transform (NTT) is an efficient algorithm that can accelerate the polynomial multiplication from <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathcal {O}(n^{2})$ </tex-math></inline-formula> to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathcal {O}(nlog(n))$ </tex-math></inline-formula> . In this brief, we present a pipelined NTT (PipeNTT) hardware architecture in FPGA to achieve high throughput with fewer hardware resources. The dataflow and the butterfly unit are optimized to minimize the latency. To fulfil the proposed dataflow, a Block RAM (BRAM) based reordering unit is designed to further reduce the hardware resource. Moreover, our architecture can also be applied to Inverse-NTT (INTT). Compared to state-of-the-art parallel designs, our design achieves a 30% lower area-time product with 3x less memory space requirement.

Stop and Look: A Novel Checkpointing and Debugging Flow for FPGAs

Hardware checkpointing enables live migration, fault recovery, and context switching, but has been difficult to achieve for FPGA applications. We detail techniques to checkpoint complex FPGA designs and develop StateMover, a new checkpoint-based debugging flow for FPGAs that combines the speed of hardware execution with the full observability and controllability of simulation. StateMover can safely stop a running design and seamlessly move its state back and forth between an FPGA and a simulator. StateMover can create complete design checkpoints even for designs that have multi-cycle I/O interfaces, contain buried state that is not accessible by FPGA readback, and use external memories. StateMover and its associated IPs allow a designer to quickly make a design checkpointable, with a small area overhead. Moving the state from/to an FPGA to/from a simulator can be performed in a few seconds for large Xilinx UltraScale FPGAs.

Digital Image Blending Using Inaccurate Addition

Inaccurate computing is found to be a high-speed, low-power and energy-efficient alternative to accurate computing for error-tolerant applications. In this context, this paper analyzes the usefulness of inaccurate computing for a digital image processing application, viz. digital image blending, which has been less explored. We analyze the use of inaccurate addition for image blending used in applications such as photo editing and computer graphics. For experimentation, we considered blending two digital images using accurate and inaccurate addition separately. We considered many inaccurate addition architectures which are suitable for implementation in both FPGA and ASIC design environments to perform a comparative analysis. We found that an inaccurate addition with an optimum inaccuracy produces a similar quality of blended image as obtained using accurate addition. The quality of blended images is quantified using standard metrics such as the peak signal-to-noise ratio and the structural similarity index measure. In particular, an inaccurate adder, M-HERLOA, was found to be preferable for image blending from the combined perspectives of quality of blended image, error metrics and design metrics. We implemented the accurate and inaccurate adders corresponding to an optimum inaccuracy in FPGA and ASIC design environments. We considered a Xilinx Artix-7 FPGA for an FPGA-based implementation and a 32/28 nm CMOS standard digital cell library for an ASIC type standard cell-based implementation. The results show that, for an FPGA-based implementation, M-HERLOA enables a reduction in delay by 13%, requires 50% fewer LUTs and 49% fewer registers and consumes 24.3% less on-chip power compared to the accurate high-speed FPGA adder while yielding a blended image of good quality. For an ASIC type standard cell-based implementation, M-HERLOA enables a reduction in delay by 64.6% (24.4%), requires 43% (82.4%), less area and dissipates 63% (67.8%) less power than the accurate carry ripple adder (carry look-ahead adder).

An OpenCL-Based FPGA Accelerator for Faster R-CNN

In recent years, convolutional neural network (CNN)-based object detection algorithms have made breakthroughs, and much of the research corresponds to hardware accelerator designs. Although many previous works have proposed efficient FPGA designs for one-stage detectors such as Yolo, there are still few accelerator designs for faster regions with CNN features (Faster R-CNN) algorithms. Moreover, CNN’s inherently high computational complexity and high memory complexity bring challenges to the design of efficient accelerators. This paper proposes a software-hardware co-design scheme based on OpenCL to implement a Faster R-CNN object detection algorithm on FPGA. First, we design an efficient, deep pipelined FPGA hardware accelerator that can implement Faster R-CNN algorithms for different backbone networks. Then, an optimized hardware-aware software algorithm was proposed, including fixed-point quantization, layer fusion, and a multi-batch Regions of interest (RoIs) detector. Finally, we present an end-to-end design space exploration scheme to comprehensively evaluate the performance and resource utilization of the proposed accelerator. Experimental results show that the proposed design achieves a peak throughput of 846.9 GOP/s at the working frequency of 172 MHz. Compared with the state-of-the-art Faster R-CNN accelerator and the one-stage YOLO accelerator, our method achieves and inference throughput improvements, respectively.