TLP-LDPC: Three-Level Parallel FPGA Architecture for Fast Prototyping of LDPC Decoder Using High-Level Synthesis

Yi-Fan Zhang, Qiang Cao + Show 1 more

https://doi.org/10.1007/s11390-022-1499-9

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Journal: Journal of Computer Science and Technology	Publication Date: Nov 30, 2022
Citations: 1

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TLP-LDPC: Three-Level Parallel FPGA Architecture for Fast Prototyping of LDPC Decoder Using High-Level Synthesis

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