Energy Efficient and Low dynamic power Consumption TCAM on FPGA

Abstract

Artificial Intelligence [AI] and networking applications extensively incorporate Field Programmable Gate Arrays [FPGA] - based Ternary Content Addressable Memories [TCAM]. Since FPGAs cannot support TCAMs, they must be emulated with SRAM-based memories, requiring FPGA resources. Compared to state-of-the-art designs, the proposed FPGA-based TCAM implementation will save significant resources. This methodology makes use of the Lookup Table RAMS (LUTRAMs), slice carry-chains, and flip-flops (FF) allowing simultaneous mapping of rules and deeper pipelining respectively. The TCAM implementation results in lower power consumption, lesser delays, and lower resource utilization. It outperformed conventional FPGA-based TCAMs in terms of energy efficiency (EE) and performance per area (PA) by at least 3.34 and 8.4 times respectively, and 56% better than existing FPGA designs. The proposed method outperforms all previous approaches due to its low dynamic power consumption when considering the huge size of TCAM emulation on SRAM-based FPGAs.