Fowler-Nordheim Tunneling Research Articles

Charge transport mechanisms of PbSnSe2 and observation of transition from direct to Fowler-Nordheim tunneling.

In this study, we report the observation of various conduction mechanisms in mechanically exfoliated PbSnSe2 based on temperature-dependent current and voltage characteristics. A transition from direct tunneling to Fowler-Nordheim tunneling in PbSnSe2 was observed at 2.63 V. At lower temperatures, the 3D Mott variable range hopping model fits the data, yielding a density of states of ∼8.80 × 1020 eV-1 cm-3 at 2 V. The values of Whop and Rhop were 64 meV and 22.7 nm, respectively, at 250 K. The Poole-Frenkel conduction was observed in the Au/PbSnSe2/Au device and the dielectric constant of PbSnSe2 was calculated to be 1.4. At intermediate voltages, a space charge limited current with an exponential distribution of traps was observed and a trap density of ∼9.53 × 1013 cm-3 and a trap characteristic temperature of 430 K were calculated for the Au/PbSnSe2/Au device.

Reformation of La0.7Sr0.3MnO3 properties by using ZnO in La0.7Sr0.3MnO3-ZnO heterostructures grown on (001) oriented Si.

Study of the available density of states (DOS) close-to-zero bias for conduction in strongly correlated electron systems, such as half-metallic La0.7Sr0.3MnO3 (LSMO) and its heterostructures, is important for fundamental and application reasons. As the DOS is proportional to the differential conductance (dI/dV), the dI/dV of a 120 Å LSMO film and its reformation in LSMO/ZnO heterostructures was investigated for different ZnO thicknesses. Unlike in conventional metals, the dI/dV of LSMO exhibits a power-law dependent zero-bias anomaly, i.e., dI/dV ∝ Vm (m ∼ 1) near zero bias in the ferromagnetic metallic state at 10 K. The growth of ZnO on LSMO reforms the linear dI/dVvs. V of LSMO near zero bias to non-linear. The exponent 'm' becomes ∼0.5 for a higher ZnO thickness, revealing increased electron-electron interactions and suppression of Kondo-like, double and superexchange interactions, which are responsible for the depression of the DOS of LSMO near zero bias. In a magnetically disordered state, i.e., around the Curie temperature, ZnO reforms the linear V-shaped dI/dV vs. V of LSMO to parabolic U-shaped dI/dVvs.V and controls the electron concentrations in the t2g-orbitals of Mn realized from the DOS simulations. Additionally, ZnO introduces a peak in the dI/dV vs. V due to Fowler-Nordheim tunnelling, and the peak voltage can be tuned by varying the ZnO thickness or temperature from 300 K to 360 K. Such functions of ZnO yield major perspectives for novel applications in thin-film-based devices.

Exploring the Surface Oxidation and Environmental Instability of 2H-/1T'-MoTe2 Using Field Emission-Based Scanning Probe Lithography.

An unconventional approach for the resistless nanopatterning 2H- and 1T'-MoTe2 by means of scanning probe lithography is presented. A Fowler-Nordheim tunneling current of low energetic electrons (E = 30-60eV) emitted from the tip of an atomic force microscopy (AFM) cantilever is utilized to induce a nanoscale oxidation on a MoTe2 nanosheet surface under ambient conditions. Due to the water solubility of the generated oxide, a direct pattern transfer into the MoTe2 surface can be achieved by a simple immersion of the sample in deionized water. The tip-grown oxide is characterized using Auger electron and Raman spectroscopy, revealing it consists of amorphous MoO3 /MoOx as well as TeO2 /TeOx . With the presented technology in combination with subsequent AFM imaging it is possible to demonstrate a strong anisotropic sensitivity of 1T'-/(Td )-MoTe2 to aqueous environments. Finally the discussed approach is used to structure a nanoribbon field effect transistor out of a few-layer 2H-MoTe2 nanosheet.

High-performance van der Waals antiferroelectric CuCrP2S6-based memristors

Layered thio- and seleno-phosphate ferroelectrics, such as CuInP2S6, are promising building blocks for next-generation nonvolatile memory devices. However, because of the low Curie point, the CuInP2S6-based memory devices suffer from poor thermal stability (<42 °C). Here, exploiting the electric field-driven phase transition in the rarely studied antiferroelectric CuCrP2S6 crystals, we develop a nonvolatile memristor showing a sizable resistive-switching ratio of ~ 1000, high switching endurance up to 20,000 cycles, low cycle-to-cycle variation, and robust thermal stability up to 120 °C. The resistive switching is attributed to the ferroelectric polarization-modulated thermal emission accompanied by the Fowler–Nordheim tunneling across the interfaces. First-principles calculations reveal that the good device performances are associated with the exceptionally strong ferroelectric polarization in CuCrP2S6 crystal. Furthermore, the typical biological synaptic learning rules, such as long-term potentiation/depression and spike amplitude/spike time-dependent plasticity, are also demonstrated. The results highlight the great application potential of van der Waals antiferroelectrics in high-performance synaptic devices for neuromorphic computing.

Probing Energy-Level Alignment in Molecular Multilayers by Frequency-Modulation Electrostatic Force Microscopy under Tapping-Mode-Combined Fowler-Nordheim Tunneling Spectroscopy.

The alignment of molecular electronic levels in a molecular multilayer is of crucial importance to realize desired functions for molecular devices. Amplitude-modulation-feedback frequency-modulation electrostatic force microscopy combined with Fowler-Nordheim tunneling spectroscopy is utilized as a probe for the energy-level alignment in an organic multilayer. Bias-dependent electrostatic force spectra were examined for bilayers including a Ru complex as a benchmark multilayer system. Electrostatic properties in the low-bias region were captured well by a single-capacitor model, which indicates weak coupling at the bilayer interface between the Ru complex and self-assembled monolayer. In contrast, in the high-bias region, significant disagreement with the expected electrostatic force was recognized for the bilayers and evaluated as the loss of electrostatic energy through the Fowler-Nordheim tunneling process. Alignment of the lowest unoccupied molecular orbital (LUMO) level of the Ru complex was determined by Fowler-Nordheim emission through resonant tunneling. These results indicate an effective method to probe level alignment at interfaces inside multilayers and to provide the partition factor β that depicts a divided electric field.

Gate leakage modeling in lateral β -Ga2O3 MOSFETs with Al2O3 gate dielectric

We present a detailed model of the static and dynamic gate leakage current in lateral β-Ga2O3 MOSFETs with an Al2O3 gate insulator, covering a wide temperature range. We demonstrate that (i) in the DC regime, current originates from Poole–Frenkel conduction (PFC) in forward bias at high-temperature, while (ii) at low temperature the conduction is dominated by Fowler–Nordheim tunneling. Furthermore, (iii) we modeled the gate current transient during a constant gate stress as effect of electron trapping in deep levels located in the oxide that inhibits the PF conduction mechanism. This hypothesis was supported by a TCAD model that accurately reproduces the experimental results.

Fabrication of a Field-Effect Transistor Based on 2D Novel Ternary Chalcogenide PdPS.

Two-dimensional (2D) palladium phosphide sulfide (PdPS) has garnered significant attention, owing to its exotic physical properties originating from the distinct Cairo pentagonal tiling topology. Nevertheless, the properties of PdPS remain unexplored, especially for electronic devices. In this study, we introduce the thickness-dependent electrical characteristics of PdPS flakes into fabricated field-effect transistors (FETs). The broad thickness variation of the PdPS flakes, ranging from 0.7-306 nm, is prepared by mechanical exfoliation, utilizing large bulk crystals synthesized via chemical vapor transport. We evaluate this variation and confirm a high electron mobility of 14.4 cm2 V-1 s-1 and Ion/Ioff > 107. Furthermore, the 6.8 nm-thick PdPS FET demonstrates a negligible Schottky barrier height at the gold electrode contact, as evidenced by the measurement of the temperature-dependent transfer characteristics. Consequently, we adjusted the Fowler-Nordheim tunneling mechanism to elucidate the charge-transport mechanism, revealing a modulated mobility variation from 14.4 to 41.2 cm2 V-1 s-1 with an increase in the drain voltage from 1 to 5 V. The present findings can broaden the understanding of the unique properties of PdPS, highlighting its potential as a 2D ternary chalcogenide in future electronic device applications.

(Best Paper Award) Aluminum Josephson Junction Formation on 200mm Wafers Using Different Oxidation Techniques

For superconducting quantum circuits with a large number of Qubits, reproducible components are crucial for reducing entanglement decoherence. Particularly for reliable industrial manufacturing on full-scale 200 mm' wafers, a very high uniformity level is required to ensure sufficient coherence times. In the present work the special focus was put on manufacturing Al/AlOx/Al Josephson junctions (JJ), which are the most important component of many quantum circuit. Fully Al-based CMOS-compatible JJ’s were produced using a double dry etch process. After patterning the first Al metallization several oxidation processes have been investigated.Static oxidation has been performed by first removing the native AlOx in a multi-chamber system with Ar milling. The final tunneling oxide was controlled by applying a specific pressure in the chamber under a pure O2 atmosphere. Afterwards, without breaking the vacuum, the second Al metallization has been deposited by sputtering. Oxide thicknesses between 1 and 2.5 nm were achieved. A full mapping of the process homogeneity will be given.On the other hand, a dynamic recipe controlled plasma oxidation process was performed, where the native AlOx was first removed by a H2 plasma followed by a defined reoxidation with an oxygen plasma. The resulting oxides had thicknesses up to 10 nm. The second Al metallization was again deposited by sputtering.Both oxidation processes were carefully studied to understand the initial oxidation process of the aluminum surface. Special attention was devoted to the non-destructive removal of the native AlOx with respect to the Al interface. Because the oxide thicknesses varied between 1 and 10 nm, the transition between direct and Fowler-Nordheim tunneling could be investigated. The process-stability on full scale 200 mm wafers and on chip size could be determined via test structures as well as the resistance variation of the Josephson junctions. Furthermore, the electrical properties of the different oxides could be measured and analyzed on wafer level. These studies provide insight into the structure and composition of the aluminum oxides and the applicability for Qubits.

Electron affinity of metal oxide thin films of TiO2, ZnO, and NiO and their applicability in 28.3 THz rectenna devices

The holy grail of achieving efficient operation of infrared (IR) rectennas continues to be the realization of a high performance rectifier. In this paper, we have fabricated metal–insulator–metal (MIM) diodes based on TiO2, ZnO, and NiO thin films using shadow mask evaporation, photolithography, and sputtering. The electron affinities of oxides have been measured by a combination of variable angle spectroscopic ellipsometry and x-ray photoelectron spectroscopy, as well as deduction from the extraction of metal/oxide barrier heights of Fowler–Nordheim tunneling plots. Our results confirm a low value for the electron affinity of NiOx of ∼2.1–2.5 eV, which correlates with the high zero-bias dynamic resistance (RD0) of ∼500 kΩ of an associated MIM diode. These values render NiOx to be unsuitable for use in a rectenna device. Better performance has been observed from diodes based on TiO2 and ZnOx films. The best rectification performance was achieved for a Au/2.6 nm ZnOx/Cr diode, scaled down to 1 μm2 device area, showing a zero-bias dynamic resistance of RD0 = 71 kΩ, zero-bias responsivity β0 = 0.28 A/W, and a coupling efficiency of ηc = 2.4 × 10−5% for rectification at 28.3 THz. The main significance of this study is that it employs a methodology whereby key parameters of the MIM stack are derived from physical measurements, which are then used to assist in the fitting of electrical current–voltage data to produce a reliable appraisal of diode performance in an IR rectenna.

(Best Paper Award, Invited) Manufacturing of Nanosheets and Multilayer Nanogaps in Silicon

Nanogap technology is the basic concept for many promising devices such as localized SOI, multichannel FETs, and resonant tunneling diodes.It will be shown that intrinsic bulk strain in single crystalline silicon can be used to create homogeneous nanogaps with a few nanometer gap distance. The strain has been created by epitaxial growth of Si1-xGex/Si multi-layer stacks on 200 mm (100) silicon wafers. The stacks were patterned by RIE to reveal the side walls for subsequent lateral etching with gaseous hydrochloric acid. In accordance with former investigations [1] we found that a selectivity up to 1000:1 for Si1-xGex/Si can be achieved for Ge-concentrations >30% and growth temperatures T<650°C. XRD measurements, SEM pictures and wagon wheel test structures prove that for the anisotropic lateral etching behavior intrinsic strain is the dominant factor. Furthermore, the crystal orientation plays a dominant role (Fig. 1). Based on this behavior multilayer nanogaps with spacings <10 nm had been fabricated.In a subsequent process nanogaps down to 5 nm have been successfully filled completely with dielectrics and/or metals by low temperature (T<450°C) plasma oxidation, LPCVD as well as ALD (Fig. 2). The resulting nanosheets can be used for device applications.Vertical diodes and lateral MOS transistors with nanogaps and nanosheets have been fabricated. Diodes with a SiO2 gap filling show perfect Fowler-Nordheim tunneling, which proves the high quality of the gap filling process. The electrical properties of nanogap-MOSFETs and various nanogap-diodes will be presented.[1] Destefanis et al., Semiconductor Sci. Technol. 23, 1 (2008) Fig. 1: Wagon wheel structure showing the etch anisotropy of 8 nm SiGe layer in Si Fig. 2: SEM cross section of a multistack of 6 SiGe layers selectively etched and completely filled with LPCVD oxide

A Fast Weight Control Strategy for Programmable Linear RAM Based on the Self-Calibrating Erase Operation

Computing-in-memory (CIM) has attracted great attention due to the need for breaking through the “memory wall”. Programmable linear random-access memory (PLRAM) for high-precision weight control is proposed to tear down the wall. However, the slow programming algorithm to tune cells limits its application in multi-level memory. Herein, a fast weight control strategy for PLRAM based on the self-calibrating erase operation is presented. The unique sidewall tunneling oxide utilized in PLRAM for bi-directional Fowler–Nordheim tunneling results in the corner-enhanced poly-to-poly tunneling effect and the self-calibrating capability during the erase process. By adopting this strategy, the efficiency of weight tuning in the PLRAM array is improved by 51% compared with the current method. The worst case is 4.9 ms for erasure, which only needs to be verified 10 times. The improvement of weight tuning efficiency means further development in CIM for PLRAM and also shows the significant prospect of PLRAM used in multi-level memory.

Polysilicon-Channel Synaptic Transistors for Implementation of Short- and Long-Term Memory Characteristics.

The rapid progress of artificial neural networks (ANN) is largely attributed to the development of the rectified linear unit (ReLU) activation function. However, the implementation of software-based ANNs, such as convolutional neural networks (CNN), within the von Neumann architecture faces limitations due to its sequential processing mechanism. To overcome this challenge, research on hardware neuromorphic systems based on spiking neural networks (SNN) has gained significant interest. Artificial synapse, a crucial building block in these systems, has predominantly utilized resistive memory-based memristors. However, the two-terminal structure of memristors presents difficulties in processing feedback signals from the post-synaptic neuron, and without an additional rectifying device it is challenging to prevent sneak current paths. In this paper, we propose a four-terminal synaptic transistor with an asymmetric dual-gate structure as a solution to the limitations of two-terminal memristors. Similar to biological synapses, the proposed device multiplies the presynaptic input signal with stored synaptic weight information and transmits the result to the postsynaptic neuron. Weight modulation is explored through both hot carrier injection (HCI) and Fowler-Nordheim (FN) tunneling. Moreover, we investigate the incorporation of short-term memory properties by adopting polysilicon grain boundaries as temporary storage. It is anticipated that the devised synaptic devices, possessing both short-term and long-term memory characteristics, will enable the implementation of various novel ANN algorithms.

2D Amorphous GaOX Gate Dielectric for β-Ga2O3 Field-Effect Transistors.

Appropriate gate dielectrics must be identified to fabricate metal-insulator-semiconductor field-effect transistors (MISFETs); however, this has been challenging for compound semiconductors owing to the absence of high-quality native oxides. This study uses the liquid-gallium squeezing technique to fabricate 2D amorphous gallium oxide (GaOX) with a high dielectric constant, where its thickness is precisely controlled at the atomic scale (monolayer, ∼4.5 nm; bilayer, ∼8.5 nm). Beta-phase gallium oxide (β-Ga2O3) with an ultrawide energy bandgap (4.5-4.9 eV) has emerged as a next-generation power semiconductor material and is presented here as the channel material. The 2D amorphous GaOX dielectric is combined with a β-Ga2O3 conducting nanolayer, and the resulting β-Ga2O3 MISFET is stable up to 250 °C. The 2D amorphous GaOX is oxygen-deficient, and a high-quality interface with excellent uniformity and scalability forms between the 2D amorphous GaOX and β-Ga2O3. The fabricated MISFET exhibits a wide gate-voltage swing of approximately +5 V, a high current on/off ratio, moderate field-effect carrier mobility, and a decent three-terminal breakdown voltage (∼138 V). The carrier transport of the Ni/GaOX/β-Ga2O3 metal-insulator-semiconductor (MIS) structure displays a combination of Schottky emission and Fowler-Nordheim (F-N) tunneling in the high-gate-bias region at 25 °C, whereas at elevated temperatures it shows Schottky emission and F-N tunneling in the low- and high-gate-bias regions, respectively. This study demonstrates that a 2D GaOX gate dielectric layer can be produced and incorporated into an active channel layer to form an MIS structure at room temperature (∼25 °C), which enables the facile fabrication of MISFET devices.

Heat Soaking for Improving Rollover From S at the Back of CIGSSe Solar Cells

A simple method of low-temperature heat-soaking (HS) treatment on copper indium gallium sulfur selenide (CIGSSe) solar cells is investigated for mitigating the rollover effect. Excessive sulfur accumulation on the backside of the CIGSSe absorber leads to downward valence band bending and forms a Schottky barrier, resulting in the rollover current–voltage characteristic at room temperature. HS treatment effectively reduces current saturation in the first quadrant of the current–voltage curves and improves cell efficiency on average by more than 6%. The depth profile on exfoliated CIGSSe absorbers from the Auger electron spectroscopy analysis demonstrates the elemental redistribution, indicating that HS treatment can change the profile gradient of sulfur. The width of sulfur accumulation is significantly reduced after HS, which enables Fowler–Nordheim tunneling by Schottky barrier width shortening. This study showcases a straightforward process and easy-to-implement strategy to reduce the second reverse diode effect caused from the sulfurization process.

Simulation of a multichannel vacuum transistor with high cut-off frequency

A multichannel vertical vacuum transistor based on the Fowler–Nordheim tunneling emission mechanism was proposed and numerically investigated. The multichannel structure was demonstrated to be effective in enhancing the drain current when compared to the traditional single-channel structure with the same device size. For example, transconductance increased from 0.42 mS of the single-channel structure to 0.86 mS of the four-channel structure. In addition, when the vacuum channel number increases, the size of a single channel decreases correspondingly, leading to a reduction in electric field intensity on the electron emission surface. Thus, the off-state current dramatically reduced by two orders of magnitude reaching10−15 A according to the simulated results. In other words, the ON/OFF drain current ratio of the multichannel structure is significantly enhanced. Furthermore, the simulation results indicate that the cut-off frequency of the multichannel device is 33% higher than that of the traditional single-channel one reaching 0.19 THz.

Combined experimental and theoretical investigation on SONOS pFLASH switch

In this paper, a new push–pull pFLASH switch is designed and fabricated based on a 110 nm eFLASH process, which includes two 2 T-pFLASH transistors and one signal transmission transistor. The pFLASH transistors are programmed and erased by band-to-band tunneling-induced hot electron and Fowler–Nordheim tunneling to realize its ‘on/off’ function, and the current of the signal transmission transistor can be effectively tuned by the drain voltage of the 2 T-pFLASH. In order to clarify the degradation mechanism of the electronic properties, first principles calculations are performed from the atomic scale. Nitrogen vacancies have been proven to play a crucial role in nitrides. In addition, the effects of vacancies on the charge retention are investigated in terms of electronic structure. The nitrogen vacancies have proven to be detrimental to the electron storage by the simulated localization energies. Therefore, this study will provide a newly designed field-programmable gate array configuration unit, whose electrical mechanisms are revealed by theoretical simulations, which can also become the design foundation for future FLASH switches.

Effects of oxygen contents on the physical properties of MgO films and carrier transport of Au/MgO/ZnO MIS diodes

MgO films with various oxygen contents were deposited on ZnO using radio-frequency magnetron sputtering, and Au/MgO/ZnO metal-insulator-semiconductor (MIS) diodes were fabricated. The effects of various oxygen contents on the physical properties of MgO and the carrier transport in MIS diodes were studied. The crystallinity of MgO films improved with increased oxygen content up to 66%; however, the crystallinity degraded upon further increase of oxygen content up to 100%. X-ray photoelectron spectroscopy showed that the oxygen vacancies were compensated by the introduced oxygen atoms; however, the excess oxygen atoms could not fill the lattice sites and were instead absorbed on the MgO surface. The optical bandgaps of MgO films increased from 5.16 to 5.22 eV for 0 and 100% oxygen content, respectively, resulted by the suppressed oxygen vacancies. The average roughness of MgO films increased from 4.02 to 6.86 nm for 0 and 100% oxygen content, respectively. As compared to MIS diodes without oxygen content, the leakage current was reduced by approximately 300 times in MIS diodes with 66% oxygen content. At a high bias voltage (V ≥ 0.4V), MIS diodes without oxygen exhibited ohmic conduction. In contrast, MIS diodes with oxygen exhibited Fowler-Nordheim tunnelling at high bias voltages. With increasing oxygen content, the tunnelling barrier height increased to its maximum of 0.46 eV in MIS diodes with 66% oxygen content. Nevertheless, the barrier height reduced to 0.29 eV for the excess oxygen content up to 100%. However, at low-bias voltages, all MIS diodes demonstrated a direct tunnelling mechanism owing to their rectangular barriers.

Gate Dielectric Current Transport Mechanisms in N-SiC Metal Oxide Semiconductor Capacitor

In this work, the voltage and temperature behavior of gate leakage current transport in SiC/SiO2 metal oxide semiconductor (MOS) capacitor was investigated. The wide range of gate voltage from-50 to 50V and temperature from 300 to 400 K, respectively uses to study the gate current conduction mechanism. Two dominant gate leakage current transport modes in SiO2 during strong accumulation with the application of positive bias were caused by Fowler–Nordheim (FN) tunneling and Poole-Frenkel (PF) emission leakage conduction. For positively biased case, FN tunneling in the range of 30-40 V dominates the gate leakage current and Poole–Frenkel conduction attributed beyond 40 V.

Novel approach for implementing ternary value logic devices showing negative differential transconductance characteristics by Fowler–Nordheim tunneling

Ternary value logic (TVL) devices are gaining attention owing to the limitations of binary devices in handling the increasing amount of information. However, the development of ternary devices has been hindered by the complex structures and use of materials lacking CMOS compatibility. This study presents a novel approach to develop ultra-simple TVL devices using thin-tunnel gate dielectrics of AlOx films and TiO2 channel layer. TVL devices are obtained by employing TiO2-based transistors with AlOx films as an oxide tunneling dielectric layer. The device exhibits typical transistor switching characteristics at low gate voltage (VG) and negative differential transconductance owing to Fowler−Nordheim tunneling current at high VG. The reversible implementation of three states, namely, ON, intermediate (INT), and OFF, with the same probability, is demonstrated with excellent reproducibility even after 200 cycles. A circuit is constructed to demonstrate the three output voltage states with respect to the input voltage by connecting the TVL device to a resistor. Additionally, the value and width of the plateau region of the INT output voltage state can be tuned by adjusting the variable resistance values. These highly simplistic TVL devices have the potential for application in low-power, highly integrated, and ultra-miniature electronic devices, thanks to their high level of CMOS compatibility.

Fowler-Nordheim tunneling mechanism Graphene/GaN ultraviolet position-sensitive detector with high precision for optoelectronic demodulation applications

As an important component of optical sensors, position-sensitive detector (PSD) plays an important role in non-contact measurement systems and is widely used in many important fields. However, the preparation and application of ultraviolet (UV) PSD are still to be studied. Herein, we propose a high precision UV PSD constructed by graphene (Gr)/GaN heterojunction (active area is 5 ×5 mm2) for the first time, and Fowler-Nordheim tunneling mechanism has been used to improve device performance. Benefiting from the FNT, under a weak light power of 0.06 mW/cm2, the PSD is able to determine the position of the UV light spot through the output photocurrent difference, displays high precision (0.16 μA/mm), excellent weak light detection capability，and good linearity without power supply. Besides, the Gr/GaN show an ultralow threshold voltage (0.132 V) of FNT. When the bias is higher than 0.132 V, photogenerated carriers will tunneling the thin insulation layer by the FNT, resulting in a multiplication of the photocurrent. Therefore, under the same power densities light irradiation (0.06 mW/cm2), the device exhibits an ultrahigh responsivity of 1.88 A/W, a remarkable detectivity of 2.71 × 1013 Jones, and a high LDR of over 99.58 at 0 V bias. More importantly, as an optoelectronic demodulator the device realizes the decoding of optical signals into electrical signals, showing great potential for application in non-contact measurement systems.