Fowler-Nordheim Tunneling Mechanism Research Articles

High emission currents and low threshold fields in multi-wall carbon nanotube-polymer composites in the vertical configuration

In this work, we present field emission characteristics of multi-wall carbon nanotube (MWCNT)-polystyrene composites at various weight fractions along the cross-section of sample. Scanning electron microscope images in cross-sectional view reveal that MWCNTs are homogeneously distributed across the thickness and the density of protruding tubes can be scaled with weight fraction of the composite film. Field emission from composites has been observed to vary considerably with density of MWCNTs in the polymer matrix. High current density of 100 mA/cm2 was achieved at a field of 2.2 V/μm for 0.15 weight fraction. The field emission is observed to follow the Fowler–Nordheim tunneling mechanism, however, electrostatic screening is observed to play a role in limiting the current density at higher weight fractions.

Nickel Nanocrystals Embedded in Metal–Alumina–Nitride–Oxide–Silicon Type Low-Temperature Polycrystalline-Silicon Thin-Film Transistor for Low-Voltage Nonvolatile Memory Application

In this work, a nickel nanocrystal (Ni-NC) assisted metal–alumina–nitride–oxide–silicon (MANOS) thin-film transistor (TFT) nonvolatile memory (NVM) was fabricated by a standard low temperature polycrystalline silicon (LTPS) TFT process. The size range and density of Ni-NCs were approximately 5–13 nm and 5 ×1011 cm-2, respectively. The programming/erasing (P/E) voltages are decreased down to -10 and +8 V, respectively, by the Fowler–Nordheim tunneling mechanism from gate injection. In this P/E voltage condition, a large memory window (∼4.2 V) was observed by current–voltage measurement. Then, the speed and voltages of P/E were measured and discussed completely. The data retention of the Ni-NC assisted MANOS-LTPS-TFT-NVM is extracted to be 1.62 V of memory window after 104 s.

Effect of postdeposition annealing on electrical properties of RF‐magnetron sputtered CeOx gate on 4H‐silicon carbide

AbstractThis research investigated the electrical characteristics of CeOx thin films deposited on n‐type 4H‐SiC via RF‐magnetron sputtering technique. Postdeposition annealing of CeOx was performed at different annealing temperatures (400, 600, 800, and 1000 °C) for 30 min in an argon ambient. The thickness of the deposited CeOx ranging from 30 to 40 nm was measured by an ellipsometer. All annealed samples showed smooth surface morphology without any physical defects. In this work, the lowest root‐mean square surface roughness was detected at samples annealed at 1000 °C. Prior to electrical characterization, all annealed samples demonstrated a positive flat‐band voltage shift indicating that negative effective oxide charge was present in the oxide layer. The sample annealed at 1000 °C revealed the lowest effective oxide charge and interface trap density as compared with other samples. The calculated interface trap density and effective oxide charge from high‐frequency capacitance–voltage curve were correlated with leakage current density and electric breakdown field. The Fowler–Nordheim tunneling mechanism only occurred in the sample annealed at 1000 °C. The leakage current density and electric breakdown field were enhanced as the postdeposition annealing increased to 1000 °C as compared with other samples.

Study of the relative performance of silicon and germanium nanoparticles embedded gate oxide in metal–oxide–semiconductor memory devices

In the present work, we have investigated a comparative performance of the silicon (Si) and germanium (Ge) nanoparticles embedded SiO2 floating gate MOS memory devices. In such devices for low applied fields, the tunneling current is dominated by the direct tunneling mechanism, whereas for higher electric fields, the Fowler–Nordheim tunneling mechanism dominates. As the device dimensions get smaller, problem arises in the conventional MOS memory devices due to the leakage through the thin tunnel oxide. This leakage can be reduced via charge trapping by embedding nanoparticles in the gate dielectric of such devices. Here one objective is to prevent the leakage due to the direct tunneling mechanism and the other objective is to reduce the write voltage, by lowering the onset voltage of the Fowler–Nordheim tunneling mechanism. Our simulations for the current voltage characteristics covered both the low and the high applied field regions. Simulations showed that both the Si and the Ge nanoparticles embedded gate dielectrics offer reduction of the leakage current and a significant lowering of the writing or programming onset voltage, compared to the pure SiO2 gate dielectric. In terms of the comparative performance, the Germanium nanoparticles embedded gate dielectric showed better results compared to the silicon nanoparticles embedded one. The results of the simulations are discussed in the light of recent experimental results.

Electrical Characteristics of Oxidized/Nitrided Zr Thin Film on Si

In this work, electrical properties of simultaneously oxidized and nitrided sputtered Zr thin film on n-type Si via N2O gas were systematically investigated and charge conduction mechanisms through the oxide were quantitatively analyzed. Effects of simultaneous oxidation and nitridation duration on the metal-oxide-semiconductor characteristics were reported. It was revealed that 15-min oxidized/nitrided sample showed the highest effective dielectric constant, breakdown field, and reliability. This was attributed to the thinnest interfacial layer, lowest total interface trap, effective oxide charge, and highest barrier height between conduction band edge of the oxide and semiconductor. Depending on the applied electric field and oxidation/nitridation duration, charges were conducted through the oxide via space-charge-limited conduction, Schottky emission, Poole-Frenkel emission, and Fowler-Nordheim tunneling mechanisms.

High permittivity Bi24Fe2O39 thin films prepared by a low temperature process

High permittivity Bi24Fe2O39 (BFO) thin films have been deposited on platinized silicon substrates by a low temperature process combining rf magnetron sputtering at room temperature and postdeposition annealing at 450 °C. A nearly pure tetragonal crystal structure with highly (201)-preferred orientation, determined by x-ray diffraction, was formed in the BFO thin film. The BFO film not only exhibits high dielectric permittivity (εr=113) and relatively low loss tangent (tan δ=0.012), but also shows a fairly small quadratic voltage coefficient of capacitance (α∼800 ppm/V2) and a small temperature coefficient of capacitance (αT∼790 ppm/°C). Moreover, the leakage current density, obeying the Fowler–Nordheim tunneling mechanism, remains at a reasonably low level with the increase in applied electric field (J∼10−6–10−4 A/cm2 under E=400 kV/cm). These attractive dielectric and electrical properties make the low temperature processed Bi24Fe2O39 thin film a promising candidate for high-k dielectric applications in silicon-based integrated circuits.

Poly-Si Nanowire Nonvolatile Memory With Nanocrystal Indium–Gallium–Zinc–Oxide Charge-Trapping Layer

This letter introduces a polycrystalline silicon (poly-Si) thin-film nonvolatile memory (NVM) with a nanocrystal (NC) indium-gallium-zinc-oxide (IGZO) charge-trapping layer. Experimental results indicate that this NVM exhibits high and symmetric program/erase speeds through the Fowler-Nordheim tunneling mechanism. The memory window loss of the NVM with NC IGZO charge-trapping layer is 25% after 104 s at 85°C due to deep quantum well, as well as high-density and deep trap sites in NC IGZO charge-trapping layer. Accordingly, a poly-Si thin-film transistor with NC IGZO charge-trapping layer is promising for NVM applications.

A Novel Self-Aligned 4-Bit SONOS-Type Nonvolatile Memory Cell With T-Gate and I-Shaped FinFET Structure

We propose a novel 4-bit self-aligned SONOS-type nonvolatile memory (NVM) cell with a T-gate and I-shaped FinFET structure for practical implementation with high storage density and better reliability. In order to obtain enhanced reliability characteristics, a modified Fowler-Nordheim tunneling mechanism is employed for programming along the channel length direction, while a band-to-band hot hole injection is used for erasing along the channel width direction. With separated paths for program and erase, improved device performance is obtained with sensing margin. In order to improve the immunity to second-bit effects, the gate-induced drain leakage current method, which is a charge detection method and highly sensitive to the locally stored charges, is employed for the reading of the stored data. In terms of the scalability, we confirmed by 2-D technology computer-aided design simulation that the proposed NVM cell with channel length <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</i> = 50 nm operates with enough sensing margin and high-density ( ~ 5 F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /bit) NVM by the crossed cell array architecture.

Abnormal current increases induced under high electric fields in asymmetrical graphite-intrinsic-diamond-graphite structures fabricated with high-quality homoepitaxial chemical-vapor-deposited diamond layers

In order to investigate an abnormal current amplification phenomenon appearing in high-quality chemical-vapor-deposited (CVD) diamond under high electric fields, we have measured current-voltage and electroluminescence (EL) characteristics of an asymmetric graphite-intrinsic-diamond-graphite (G-ID-G) structure specially fabricated with a high-quality homoepitaxial CVD diamond layer. The G-ID-G structure included a flat G layer and a protrusive G layer, both of which were thin graphitic ones suitably formed on the surface layers of the CVD diamond using well-focused 30 keV Ga ions. The measured current-voltage data demonstrated that the voltages yielding the same currents were substantially lower when the protrusive G layer was positively biased. It turned out that the currents were reproduced with a sum of two components, namely, one injected from the positively biased G layer to the diamond, probably due to the Fowler–Nordheim tunneling mechanism, and the other yielding abnormal current increases in the diamond under high fields of the order of 106 V/cm. Furthermore, substantial EL was observed only in the voltage region the abnormal current increases obviously occurred. These facts and field calculations using a finite element method suggest both hole injections from the G layer to the ID layer and high-field-induced excitations of valence electrons in the ID layer to the conduction bands by the impact ionization process. An increase in the applied voltage by 15% was estimated to give a hundredfold amplification of the current. The present analysis of the measured data is discussed in detail in relation to the local structure of the high-quality diamond.

Electrical Properties of Pulsed Laser Deposited Y[sub 2]O[sub 3] Gate Oxide on 4H–SiC

Yttrium oxide (Y 2 0 3 ) has been successfully deposited on n-type 4H-SiC substrates using pulsed laser deposition. The effects of postdeposition annealing temperature (400, 500, and 600°C) on the electrical properties of the Y 2 O 3 gate oxide have been studied in comparison with the as-deposited sample. The sample annealed at 600°C possessed the highest dielectric breakdown field of ∼6.5 MV cm -1 at 10- 6 A cm -2 , resulting from the lowest interface trap density and total interface trap density. The Fowler-Nordheim tunneling mechanism has been investigated on all samples and the highest value of barrier height extracted between the semiconductor and oxide conduction band edges was 2.67 eV.

Ruthenium oxide metal nanocrystal capacitors with high- κ dielectric tunneling barriers for nanoscale nonvolatile memory device applications

The ruthenium oxide metal nanocrystals embedded in high- κ HfO 2/Al 2O 3 dielectric tunneling barriers prepared by atomic layer deposition in the n-Si/SiO 2/HfO 2/ruthenium oxide (RuO x )/Al 2O 3/Pt memory capacitors with a small equivalent oxide thickness of 8.6 ± 0.5 nm have been investigated. The RuO x metal nanocrystals in a memory capacitor structure observed by high-resolution transmission electron microscopy show a small average diameter of ∼7 nm with high-density of >1.0 × 10 12/cm 2 and thickness of ∼3 nm. The ruthenium oxide nanocrystals composed with RuO 2 and RuO 3 elements are confirmed by X-ray photoelectron spectroscopy. The enhanced memory characteristics such as a large memory window of Δ V ≈ 12.2 V at a sweeping gate voltage of ±10 V and Δ V ≈ 5.2 V at a small sweeping gate voltage of ±5 V, highly uniform and reproducible, a large electron (or hole) storage density of ∼1 × 10 13/cm 2, low charge loss of <7% (Δ V ≈ 4.2 V) after 1 × 10 4 s of retention time are observed due to the formation of RuO x nanocrystals after the annealing treatment and design of the memory structure. The charge storage in the RuO x nanocrystals under a small voltage operation (∼5 V) is due to the modified Fowler–Nordheim tunneling mechanism. This memory structure can be useful for future nanoscale nonvolatile memory device applications.

A Fully Differential Rail-to-Rail CMOS Capacitance Sensor With Floating-Gate Trimming for Mismatch Compensation

This paper presents a fully differential capacitance sensor employing the CBCM technique to map differential input capacitances into rail-to-rail differential output voltages. The circuit has been designed for measuring capacitances in the plusmn25-fF range, appropriate for sensing live cells using on-chip microelectrodes. An array architecture based on a shielded current routing bus has been developed for incorporating the capacitance measurement circuit into sensor arrays, with each pixel comprising four minimum-size digital transistors, enabling high-density integration. In addition to improving spatial resolution, the shielded current bus also eliminates the need for individual pixel calibration, conserves sensor evaluation speed, and provides protection from junction leakage. The sensor employs a 3-phase clocking scheme that enables on-chip gain tuning. The paper also presents a modified version of the sensor circuit incorporating floating-gate transistors for mismatch compensation and output offset cancellation, performed using a combination of impact-ionized channel hot electron injection and Fowler-Nordheim tunneling mechanisms. Chips comprising both versions of the sensor circuits in test arrays employing the shielded current routing bus were fabricated in a commercially available 2-poly, 3-metal, 0.5-mum CMOS process. The sensor operation was demonstrated by measuring on-chip test capacitances comprising single and interdigitated metal electrodes, configured using different capacitance compensation schemes. The differential sensor in combination with the shielded current bus exhibits a maximum sensitivity of 200 mV/fF, a resolution of 15 aF, and an output dynamic range of 65 dB.

A Charge-Based Low-Power High-SNR Capacitive Sensing Interface Circuit

This paper describes a low-power approach to capacitive sensing that achieves a high signal-to-noise ratio. The circuit is composed of a capacitive feedback charge amplifier and a charge adaptation circuit. Without the adaptation circuit, the charge amplifier only consumes 1 μW to achieve the audio band SNR of 69.34dB. An adaptation scheme using Fowler-Nordheim tunneling and channel hot electron injection mechanisms to stabilize the DC output voltage is demonstrated. This scheme provides a very low frequency pole at 0.2Hz. The measured noise spectrums show that this slow-time scale adaptation does not degrade the circuit performance. The DC path can also be provided by a large feedback resistance without causing extra power consumption. A charge amplifier with a MOS-bipolar pseudo-resistor feedback scheme is interfaced with a capacitive micromachined ultrasonic transducer to demonstrate the feasibility of this approach for ultrasound applications.

Study of tunneling mechanism of Au nanocrystals in HfAlO matrix as floating gate memory

A floating gate memory structure containing HfAlO control gate, self-organized Au nanocrystals (NCs), and a HfAlO tunnel layer has been fabricated by pulsed-laser deposition. Owing to the charging effects of Au NCs, a significant threshold voltage shift has been obtained and the memory window up to 10.0V and stored charge density up to 1×1014∕cm2 has been achieved. Fowler–Nordheim tunneling mechanism is used to analyze the capacitance-voltage characteristics of the trilayer memory structure, and it is found that higher density and smaller size of the Au NCs result in a higher tunneling coefficient and a larger memory window.

Si-Nanowire Based Gate-All-Around Nonvolatile SONOS Memory Cell

This letter presents a high-speed silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory cell in gate-all-around Si-nanowire (NW) architecture, which is fabricated by using a top-down process technology. The NW cell exhibits faster program and erase (P/E) speed compared to the corresponding planar device; 1 mus for programming and 1 ms for erasing at VGS = plusmn11 V with a threshold voltage shift DeltaVTH of 2.6 V using the Fowler-Nordheim tunneling mechanism. At these P/E conditions, the planar device does not show appreciable change. The improvement is originated from: 1) increased electric field at the Si-SiO2 interface; 2) reduced effective tunnel barrier width; and 3) low electric field in the blocking oxide, as analyzed through simulation. In addition, good data retention makes the NW-based SONOS cell a potential candidate for future high-speed low-voltage NAND-type nonvolatile Flash memory applications.

Polyoxometalate-Based Layered Structures for Charge Transport Control in Molecular Devices

Hybrid organic-inorganic films consisted of molecular layers of a Keggin-structure polyoxometalate (POM: 12-tungstophosphoric acid, H(3)PW(12)O(40)) and 1,12-diaminododecane (DD) on 3-aminopropyl triethoxysilane (APTES)-modified silicon surface, fabricated via the layer-by-layer (LBL) self-assembly method are evaluated as molecular materials for electronic devices. The effect of the fabrication process parameters, including primarily compositions of deposition solutions, on the structural characteristics of the POM-based multilayers was studied extensively with a combination of spectroscopic methods (UV, FTIR, and XPS). Well-characterized POM-based films (both single-layers and multilayers) in a controlled and reproducible way were obtained. The conduction mechanisms in single-layered and multilayered structures were elucidated by the electrical characterization of the produced films supported by the appropriate theoretical analysis. Fowler-Nordheim (FN) tunneling and percolation mechanisms were encountered in good correlation with the structural characteristics of the films encouraging further investigation on the use of these materials in electronic and, in particular, in memory devices.

Atomic-layer-deposited HfO2 on In0.53Ga0.47As: Passivation and energy-band parameters

Atomic-layer-deposited high κ dielectric HfO2 films on air-exposed In0.53Ga0.47As∕InP (100), using Hf(NCH3C2H5)4 and H2O as the precursors, were found to have an atomically sharp interface free of arsenic oxides, an important aspect for Fermi level unpinning. A careful and thorough probing, using high-resolution angular-resolved x-ray photoelectron spectroscopy (XPS) with synchrotron radiation, however, observed the existence of Ga2O3, In2O3, and In(OH)3 at the interface. The current transport of the metal-oxide-semiconductor capacitor for an oxide 7.8nm thick follows the Fowler–Nordheim tunneling mechanism and shows a low leakage current density of ∼10−8A∕cm2 at VFB+1V. Well behaved frequency-varying capacitance-voltage curves were measured and an interfacial density of states of 2×1012cm−2eV−1 was derived. A conduction-band offset of 1.8±0.1eV and a valence-band offset of 2.9±0.1eV have been determined using the current transport data and XPS, respectively.

Study of AlGaN/GaN MOSHEMT device with Al2O3 insulating film

On the basis of AlGaN/GaN HEMT，the AlGaN/GaN MOSHEMT device was fabricated with Al2O3 insulating film for the first time, which was deposited by ALD.The X-ray photoelectron spectroscopy measurements showed successful deposition of Al2O3 layer on the AlGaN/GaN film. The results of Schottky capacitance，I-V characteristics and DC transfer characteristics measurement showed that the interface state density between the AlGaN film and the Al2O3 insulating film was fairly low and the MOSHEMT device showed successful gate control of drain current up to VGS=+3V and achieved drain saturation current of 800mA/mm，which was much larger than that of the HEMT device. Furthermore，the gate leakage current of MOSHEMT is two orders lower in the reverse bias condition as compared with the Schottky gate structure，which increased the device breakdown voltage，while the leakage current was governed by the Fowler-Nordheim tunneling mechanism.

Electrical performance of Al2O3 gate dielectric films deposited by atomic layer deposition on 4H-SiC

Stoichiometric and pure Al2O3 gate dielectric films were grown on n-type 4H-SiC by a thermal atomic layer deposition process. The electrical properties of both amorphous and epitaxial Al2O3 films were studied by capacitance-voltage and current-voltage measurements of metal-oxide-semiconductor capacitors. A dielectric constant of 9 and a flatband voltage shift of +1.3V were determined. A leakage current density of 10−3A∕cm2 at 8MV∕cm was obtained for the amorphous Al2O3 films, lower than that of any high-κ gate oxide on 4H-SiC reported to date. A Fowler-Nordheim tunneling mechanism was used to determine an Al2O3∕4H-SiC barrier height of 1.58eV. Higher leakage current was obtained for the epitaxial γ-Al2O3 films, likely due to grain boundary conduction.

C O 2 laser rapid-thermal-annealing SiOx based metal-oxide-semiconductor light emitting diode

Structural damage enhanced near-infrared electroluminescence (EL) of a metal-oxide-semiconductor light emitting diode (MOSLED) made on SiOx film with buried nanocrystallite Si after CO2 laser rapid thermal annealing (RTA) at an optimized intensity of 6kW∕cm2 for 1ms is demonstrated. CO2 laser RTA induced oxygen-related defects are capable of improving Fowler-Nordheim tunneling mechanism of carriers at metal/SiOx interface. The CO2 laser RTA SiOx film reduces Fowler-Nordheim tunneling threshold to 1.8MV∕cm, facilitating an enhanced EL power of an indium tin oxide/SiOx∕p-Si∕Al MOSLED up to 50nW at a current density of 2.3mA∕cm2.