This paper presents a new CMOS four-quadrant low voltage and low power analog multiplier circuit in voltage mode. In the proposed analog multiplier, transistors are biased in weak inversion by driving them at bulk terminals. The proposed design has fully differential ended output. Input signal ranges are ±40mV and all transistors have the equal sizes. Simulation results have been presented by HSPICE simulator in 0.18μm standard CMOS technology to confirm the operation of the circuit. The results show that the proposed analog multiplier has several advantages in comparison with other analog multipliers.