Ultra-shallow Junction Formation Research Articles

High-resolution Rutherford backscattering spectrometry with an optimised solid-state detector

Rutherford Backscattering Spectrometry (RBS) is a powerful ion beam analysis technique in frequent use within materials science. The recent emergence of targets incorporating complex features such as ultra-scaled diffusion barriers and isotopically-enriched films has started to push the limits of the technique, necessitating the expanded use of systems with a higher energy resolution. The increased cost and complexity of these systems based on already well-established schemes may present a barrier to their more widespread adoption. Here, we present an RBS detection system specifically designed for simple integration into existing nuclear probe infrastructure, but with a considerably higher energy resolution than a standard passivated planar detector. We employ a modified silicon p–i–n photodiode integrated within an optimised in-vacuum preamplifier to achieve a relative energy resolution of 3 × 10−3 with 2.2 MeV He+ ions. In a glancing angle geometry, this corresponds to a depth resolution of ∼1.5nm and a mass resolution of <1u from light elements up to Cu. We demonstrate the use of this detector to measure the thermal diffusion of near-surface As implants in a Si substrate, important for the formation of ultra-shallow junctions; and the residual 29Si concentration in an isotopically enriched 28Si specimen, a promising platform for quantum computation.

Conformal and Ultra Shallow Junction Formation Achieved Using a Pulsed-Laser Annealing Process Integrated With a Modified Plasma Assisted Doping Method

Recently, a shallow and conformal doping profile is required for promising 3D structured devices. In this study, we deposited the dopant phosphorus (P) using modified plasma assisted doping (PaD) followed by an annealing process to electrically activate the dopants. A rapid thermal annealing process (RTP) was the first approach tested for activation but it resulted in a deep junction (>35 nm). To reduce the junction depth, we tried the flash lamp annealing process (FLP) to shorten the annealing time. We also predicted the annealing temperature by numerical thermal analysis, which reached 1,020 °C. However, the FLP resulted in a deep junction (~ 30 nm), which was not shallow enough to suppress short channel effects. Since an even shorter annealing process was required to form a ultra-shallow junction, we tried the laser annealing process (LAP) as a promising alternative. The LAP, which had a power density of 0.3 J/cm2, increased the surface temperature up to 1,100 °C with a shallow isothermal layer. Using the LAP, we achieved a USJ with an activated surface dopant concentration of $3.86\times 10 ^{19}$ cm−3 and a junction depth of 10 nm, which will allow further scaling-down of devices.

Effects of oxygen-inserted layers on diffusion of boron, phosphorus, and arsenic in silicon for ultra-shallow junction formation

The effects of oxygen-inserted (OI) layers on the diffusion of boron (B), phosphorus (P), and arsenic (As) in silicon (Si) are investigated, for ultra-shallow junction formation by high-dose ion implantation followed by rapid thermal annealing. The projected range (Rp) of the implanted dopants is shallower than the depth of the OI layers. Secondary ion mass spectrometry is used to compare the dopant profiles in silicon samples that have OI layers against the dopant profiles in control samples that do not have OI layers. Diffusion is found to be substantially retarded by the OI layers for B and P, and less for As, providing shallower junction depth. The experimental results suggest that the OI layers serve to block the diffusion of Si self-interstitials and thereby effectively reduce interstitial-aided diffusion beyond the depth of the OI layers. The OI layers also help to retain more dopants within the Si, which technology computer-aided design simulations indicate to be beneficial for achieving shallower junctions with lower sheet resistance to enable further miniaturization of planar metal-oxide-semiconductor field-effect transistors for improved integrated-circuit performance and cost per function.

Ultra-Shallow Junction Formation by Monolayer Doping Process in Single Crystalline Si and Ge for Future CMOS Devices

We focused on the damage-free monolayer doping (MLD) method starting from a chemical reaction of molecules on Si and Ge surfaces and applied it to 3D MOSFET device fabrication. MLD methods were verified by different material analysis, such as XPS and Raman spectroscopy. For a Si-based FinFET structure, compared to the device with ion implantation, the short channel effect of source and drain (SD) extension regions formed by MLD are improved. The shallower SD extension regions formed by low-temperature microwave annealing (MWA) are expected to the device showing better electrical properties than deeper ones formed by RTA. In addition, formation of the n- and p-type doping in Ge by MLD was also investigated. Even after annealing at 800°C for 300 sec by RTA, the p-type doping still exhibits a low surface doping concentration due to the low diffusion coefficient of B in Ge and surface diffusion limitations at the MLD/Ge interface. By using a combination of RTA and CO2 laser spike annealing (LSA), MLD n-type doping in Ge are formed with junction depths of ≈15 nm, and peak concentration of ≈ 6 × 1020 atoms/cm3. The dopant activation for the MLD-doped channels of Ge junctionless FinFETs (JLFinFETs) is improved after the additional CO2 LSA.

Effect of number of laser pulses on p+/n silicon ultra-shallow junction formation during non-melt ultra-violet laser thermal annealing

We investigate the effect of the number of laser pulses on the formation of p+/n silicon ultra-shallow junctions during non-melt ultra-violet laser (wavelength, 355nm) annealing. Through surface peak temperature calculating by COMSOL Multiphysics, the non-melt laser thermal annealing is performed under the energy density of 130mJ/cm2. We demonstrate that increasing the number of laser pulses without additional pre-annealing is an effective annealing method for achieving good electrical properties and shallow junction depth by analyzing sheet resistance and junction depth profiles. The optimal number of laser pulses is eight for achieving a high degree of activation of dopant without further increase of junction depth. We have also explained the improved electrical characteristics of the samples on the basis of fully recovered crystallinity as revealed by Raman spectroscopy. Thus, it is suggested that controlling the number of laser pulses with moderate energy density is a promising laser annealing method without additional pre-annealing.

Prediction of low-energy boron doping profile for ultrashallow junction formation by hybrid molecular dynamics method

Our original hybrid method combining tight-binding quantum chemical and classical molecular dynamics was first applied to the low-energy doping process of boron into a silicon substrate, which has a depth of more than 10 nm that is needed to evaluate an ultrashallow junction position. Tight-binding quantum chemical molecular dynamics calculation was used for an injected boron atom and surrounding silicon atoms within a sphere with a radius of 0.5 nm centered at the boron atom. This method is advantageous in treating the many-body collision effect and electron–electron interaction, which are more important in low-energy doping, compared with the Monte Carlo method with binary collision approximation. A comparison with a plasma doping experiment was also carried out. The junction positions were 6.2 nm for boron doping at an initial kinetic energy of 200 eV in the simulation results and 6.4 nm for 200 eV in the experimental results. Good agreement between simulation and experimental results indicates that our hybrid molecular dynamics method is applicable to doping profile prediction in a silicon structure with a depth of more than 10 nm that is needed to evaluate ultrashallow junction formation.

Physically Based Analytical Modeling of 2D Electrostatic Potential for Symmetric and Asymmetric Double Gate Junctionless Field Effect Transistors in Subthreshold Region

When traditional planar Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) are scaled, they lose the gate control over the channel charges because the charges are partially controlled by the drain/source depletion regions [1]. Several types of nonplanar structures with multiple-gated configuration have been proposed for providing better electrostatic control of the charges in the channel region; therefore reducing short-channel effects (SCEs) – like subthreshold slope (SS) degradation, threshold voltage roll-off (TVRO) and drain-induced barrier lowering (DIBL) [2]. However, further miniaturization of such devices becomes quite challenging because of the formation of ultra-shallow and abrupt junctions which requires novel doping and special annealing techniques. Junctionless Field Effect Transistors (JLFETs) have recently been proposed to provide a solution for this issue which typically consist of the source and drain having same doping type as the channel and the thickness of the silicon body thin enough to make the silicon body fully depleted when switched off [3]. Therefore, JLFETs need neither lateral abrupt doping, nor high thermal budget, thus making manufacturing simpler. Besides that JLFETs provide reduced SCEs, an excellent SS, a very low leakage current and high Ion/Ioff ratio compared to conventional MOSFETs [4]. A number of studies based on simulations and analytical solutions have been performed to anticipate the performance of symmetric JLFETs [5-7]. However, a complete analytical treatment for both symmetric and asymmetric double gate JLFETs is necessary to make a comparative study of their performance. In this work, we propose a physically based analytical model of 2D electrostatic potential in the subthreshold region applicable for different structures of JLFET. The schematic cross-sectional view of an n-type double gate JLFET considered in this work is shown in figure 1. The thickness of the source and drain regions are assumed to be zero for the sake of simplicity of modeling. The source and drain electrodes are shown to be present at the two side of the bulk silicon layer which is heavily doped with n-type impurity. Figure 2 shows the analytical expression of 2D electrostatic potential in the channel region of double gate JLFET. In order to obtain the equation, we analytically solve 2D Poisson’s equation in the channel region using cubic approximation with appropriate boundary conditions. This analytical solution is valid in the subthreshold region of operation for both symmetric and asymmetric double gate JLFETs with similar and dissimilar gate bias configurations. αy and βy in the equation depend on the physical parameters and position along Y-axis which are not shown in the figure. Figure 3 and 4 show the surface plot of 2D channel potential distribution for symmetric and asymmetric double gate n-channel JLFET respectively. In this work we consider symmetric structure with P+ polysilicon as both gate electrodes and asymmetric structure with P+ polysilicon and Ni metal as top and bottom gate electrodes respectively. For a fully depleted double gate JLFETs, the threshold voltage is reached when a portion of the channel is no longer depleted, such that bulk current flows through a neutral path. The threshold voltage of symmetric and asymmetric JLFETs is obtained using the 2D potential model shown in figure 2 by determining the gate voltage for which minimum channel potential along source to drain direction at a particular depth of the silicon channel along the top to bottom gate direction becomes zero. DIBL of JLFETs can be defined as the lowering in the threshold voltage due to the increase in the drain voltage. In this work DIBL is also calculated by varying Vds from 0.1V to 1V. Figure 5 and 6 exhibits the variation of TVRO and DIBL with the channel length of symmetric and asymmetric double gate JLFETs respectively. The asymmetric structure demonstrates smaller TVRO and less DIBL than the symmetric structure when the devices are shrunk into a deep-submicrometer regime. In this work we have obtained a 2D channel potential model in subthreshold region for double gate JLFETs. The analytical potential model is further used to determine TVRO and DIBL of symmetric and asymmetric JLFETS so that performance comparison of subthreshold characteristics can be made between different structures of JLFET.

Fast and Accurate in-Line Monitor of Boron Implantation Energy and Dose by Spectroscopic Ellipsometry

Boron is a specified dopant applied at semiconductor manufacturing, which used for ultra-shallow junction (USJ) formation and stable SiGe stressed channel configuration at advanced generation. Aggressive device scaling over the last decade leads the precise implantation control much important and critical. In this paper, a non-destructive and fast technology for inline Boron implanted depth and dose concentration measurement was presented using Spectroscopic Ellipsometry (SE) methodology. Excellent correlation with SIMS reference result achieved. Further, the implanted processes quene time (Q-time) issue was also be considered for stable production monitor in foundry side. The metrology theory could extend to other doping species at medium and low energy application field.

Stimulated oxygen impurity gettering under ultra-shallow junction formation in silicon

Ultra-shallow junctions were formed by low-energy As ion implantation followed by furnace annealing. It was found that a significant amount of oxygen is redistributed from the silicon bulk to the As-implanted region. Using a marker layer created by implantation of 18O isotope, it is confirmed that a large number of interstitial oxygen atoms are transferred from the bulk of Si wafer to the surface during dopant activation annealing, which leads to an increase of the surface oxide thickness. Estimation of the oxygen diffusivity in silicon during the 950 °C anneal, yields a value close to 1 × 10−10 cm2 s−1 which is more than an order of magnitude larger than the literature value which is close to 7 × 10−12 cm2 s−1.

NMOS Low Boron Activation in Pre-Amorphise Silicon

The high demand of smaller and compact size of MOSFETs has leads to desirable for ultra shallow junction formation with low sheet resistance and good electrical performances. These two characteristics are required to suppress short channel effects and to increase the efficiency of device. In this paper, Pre-amorphise implantation (PAI) PMOS with different doses of Boron and the basic PMOS structure are done by using ATHENA and the performance of devices is compared by using ATLAS software package from Silvaco TCAD. Comparison done in electrical characteristic, I-V curve Ion and Ioff has showed PMOS with PAI technology with low boron doses resulted in increasing electrical performance characteristic.

Modeling of junction formation in scaled Si devices

In this article, modeling of junction formation in scaled Si device is shown. An atomistic kinetic Monte Carlo (KMC) diffusion modeling is used for the analysis of dopant diffusion and defects during shallow junction formation processes. Dopant diffusion and defect evolution during sub-millisecond non-melt laser annealing (NLA) are studied in both experiments and an atomistic kMC diffusion modeling. Pre-amorphization implant is often used for ultra shallow junction formation. It is shown that Solid Phase Epitaxial Regrowth (SPER) annealing stage plays an important role for dopant diffusion in junction formation process. As Ge implant energy is increased, damage structure and IV composition of Amorphous Pockets are changed and this affects the dopant diffusion and activation behavior. KMC simulations show that B, As deactivation is induced by the formation of dopant-defect complexes, such as B n I m , As n V m , As n I m , As n , during millisecond annealing time range. Both experiments and KMC show that defect evolution during millisecond annealing time range. Fluorine, Carbon co-implant effects are also modeled using KMC.

Peculiarities of the Impurity Redistribution under Ultra-Shallow Junction Formation in Silicon

Ultra-shallow junctions (USJs) were formed by low-energy As ion implantation with the subsequent furnace annealing. It was found that the significant amount of oxygen is redistributed from the silicon bulk to the arsenic-implanted region. We present the effect of oxygen gettering at the creation of arsenic-doped USJs using the marker layer created by ion implantation of 18O isotope.

Modeling of defects, dopant diffusion and clustering in silicon

Ion implantation is a very well established technique to introduce dopants in semiconductors. This technique has been traditionally used for junction formation in integrated circuit processing, and recently also in solar cells fabrication. In any case, ion implantation causes damage in the silicon lattice that has adverse effects on the performance of devices and the efficiency of solar cells. Alternatively, damage may also have beneficial applications as some studies suggest that small defects may be optically active. Therefore it is important an accurate characterization of defect structures formed upon irradiation. Furthermore, the technological evolution of electronic devices towards the nanometer scale has driven the need for the formation of ultra-shallow and low-resistive junctions. Ion implantation and thermal anneal models are required to predict dopants placement and electrical activation. In this article, we review the main models involved in process simulation, including ion implantation, evolution of point and extended defects and dopant-defect interactions. We identify different regimes at which each type of defect is more relevant and its inclusion in the models becomes crucial. We illustrate in some examples the use of atomistic modeling techniques to gain insight into the physics involved in the processes as well as the relevance of the accuracy of models.

NMOS Performance of Low Boron Activation on Group V for Ultra-Shallow Junction Formation

Fabrication of ultra shallow junctions with low contact resistances is desired to advance current CMOS technology. The low Boron activation on Group V for ultra shallow junction formation will makes the chip fabrication works effectively. SilvacoTCAD (Technology Computer Aided Design) manages simulation tasks and analyzing simulation results when ultra-shallow junction formation is using low-boron activation on Phosphorus, Antimony and Arsenic.A stimulate process like implantation, diffusion and dopant activation and epitaxial growth in different semiconductor materials has been analyzed as well as investigate the effects of energy of boron ion beams on ultra shallow junction formation.As a result, the electrical characteristics of NMOS structure by obtaining graph of IDVGSand IDVDShas been studied when there are variations in junction length (Xj), and gatelength (Lg).

Exploring the Limits of N-Type Ultra-Shallow Junction Formation

Low resistivity, near-surface doping in silicon represents a formidable challenge for both the microelectronics industry and future quantum electronic devices. Here we employ an ultra-high vacuum strategy to create highly abrupt doping profiles in silicon, which we characterize in situ using a four point probe scanning tunnelling microscope. Using a small molecule gaseous dopant source (PH3) which densely packs on a reconstructed silicon surface, followed by encapsulation in epitaxial silicon, we form highly conductive dopant sheets with subnanometer control of the depth profiles. This approach allows us to test the limits of ultra-shallow junction formation, with room temperature resistivities of 780 Ω/□ at an encapsulation depth of 4.3 nm, increasing to 23 kΩ/□ at an encapsulation depth of only 0.5 nm. We show that this depth-dependent resistivity can be accounted for by a combination of dopant segregation and surface scattering.

Ultra-shallow junctions formed using microwave annealing

Microwave annealing is shown to be viable for achieving low thermal budget formation of ultra-shallow junctions. Regrowth of a 10 nm thick amorphous Si layer that is generated during a Ge amorphization process prior to BF2 or As dopant implantation proceeds at rates up to 0.53 nm/min for BF2 and up to 0.33 nm/min for As at 370 °C. The fraction of electrical activation for implanted dopants is as high as 13% for BF2 and 32% for As with negligible diffusion at 540 °C.

Analysis of USJ formation with combined RTA/laser annealing conditions for 28 nm high-k/metal gate CMOS technology using advanced TCAD for process and device simulation

TCAD process and device simulations are used to gain physical understanding for the integration of laser-annealed junctions into a 28nm high-k/metal gate first process flow. Spike-RTA (Rapid Thermal Annealing) scaling used for transient enhanced diffusion (TED) suppression and shallow extension formation is investigated. In order to overcome the performance loss due to a reduced RTA, laser anneal (lsa) is introduced after Spike-RTA to form highly activated and ultra shallow junctions (USJs). In this work, the impact of different annealing conditions on the performance of NMOS and PMOS devices is investigated in terms of Vth and Ion/Ioff, considering lateral dopant diffusion and activation.

Formation of Co-implanted Silicon Ultra-Shallow Junctions for Low Thermal Budget Applications

We present a systematic study to create ultra-shallow junctions in n-type silicon substrates and investigate both pre- and post-annealing processes to create a processing strategy for potential applications in nano-devices. Starting wafers were co-implanted with indium and C atoms at energies of 70 keV and 10 keV, respectively. A carefully chosen implantation schedule provides an abrupt ultra-shallow junction between 17 and 43 nm with suppressed sheet resistance and appropriate retained sheet carrier concentration at low thermal budget. A defect doping matrix, primarily the behavior and movement of co-implant generated interstitials at different annealing temperatures, may be engineered to form sufficiently activated ultra-shallow devices.

Nonthermal illumination effects on ultra-shallow junction formation

In this letter, we present direct and unambiguous experimental evidence for nonthermal illumination effects in boron or arsenic implanted silicon. Both, dopant diffusion and activation vary significantly with illumination. Depending on annealing temperature, diffusion is either enhanced or inhibited. The results have significant implications for modeling and formation of ultrashallow junctions.

Effect of Fluorine Co-Implant on Boron Diffusion in Germanium Preamorphized Silicon During Post-LSA Rapid Thermal Annealing

Fluorine co-implant has been shown to reduce boron transient enhanced diffusion and deactivation when coupled with conventional spike rapid thermal anneals (RTA). For ultrashallow junction formation beyond the 45 nm technology node, non-melt laser spike anneal (LSA) is a promising diffusion-less annealing candidate. In this paper, the effect of fluorine co-implant on boron diffusion during LSA and the subsequent post-LSA thermal budget is evaluated. Silicon wafers were implanted with germanium, fluorine, and subsequently boron ions. Non-melt LSA was carried out at a temperature range from 1150 to 1350°C, followed by RTA at 825°C for 30 s. Secondary ion mass spectrometry confirms that in the presence of fluorine, retarded boron diffusion is observed at LSA temperatures below 1250°C. As the LSA temperature is increased or when a subsequent soak RTA is carried out, enhanced boron diffusion is observed. The reduced boron diffusivity at LSA temperatures below 1250°C is attributed to the efficient capture of interstitials released from the end-of-range defects by fluorine-vacancy clusters during the millisecond anneal. As the thermal budget is increased, excess interstitials caused by the fluorine implant are released, thus increasing the boron diffusion.